+2017-11-15 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/noextreg.s: Add tests for VEX-encoded GPR
+ insns with VEX.W set.
+ * testsuite/gas/i386/noextreg.d: Adjust expectations.
+
2017-11-15 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/noextreg.{s,d}: New.
Disassembly of section .text:
0+ <ix86>:
+[ ]*[a-f0-9]+: c4 e2 78 f2 00 andn \(%eax\),%eax,%eax
+[ ]*[a-f0-9]+: c4 e2 f8 f2 00 andn \(%eax\),%eax,%eax
+[ ]*[a-f0-9]+: 8f e9 78 01 20 tzmsk \(%eax\),%eax
+[ ]*[a-f0-9]+: 8f e9 f8 01 20 tzmsk \(%eax\),%eax
+[ ]*[a-f0-9]+: 8f e9 78 12 c0 llwpcb %eax
+[ ]*[a-f0-9]+: 8f e9 f8 12 c0 llwpcb %eax
[ ]*[a-f0-9]+: c4 e3 79 68 00 00 vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
[ ]*[a-f0-9]+: c4 e3 79 68 00 0f vfmaddps %xmm0,\(%eax\),%xmm0,%xmm0
[ ]*[a-f0-9]+: c3 ret[ ]*
.intel_syntax noprefix
.text
ix86:
+ andn eax, eax, [eax]
+ .code64
+ andn rax, rax, [rax]
+ .code32
+
+ tzmsk eax, [eax]
+ .code64
+ tzmsk rax, [rax]
+ .code32
+
+ llwpcb eax
+ .code64
+ llwpcb rax
+ .code32
+
vfmaddps xmm0, xmm0, [eax], xmm0
.byte 0xc4, 0xe3, 0x79, 0x68, 0x00, 0x0f # vfmaddps xmm0, xmm0, [eax], xmm0
+2017-11-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
+ determine GPR register set.
+
2017-11-15 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (VEXI4_Fixup, VexI4): Delete.
names = names_xmm;
break;
case dq_mode:
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
MODRM_CHECK;
codep++;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
{
const char **names;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;