sim,arch: Collapse the ISA specific versions of m5Syscall.

The x86 version doesn't do anything x86 specific, and so can be used
generically in sim/pseudo_inst.(hh|cc)

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/alpha/pseudo_inst.hh b/src/arch/alpha/pseudo_inst.hh
index 9f8b508c29d1e04fe5990623314c939f55c9f616..f15d0f572a556f4a6f5336b4bae1b1e036c7d9d4 100644 (file)
--- a/src/arch/alpha/pseudo_inst.hh
+++ b/src/arch/alpha/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_ALPHA_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace AlphaISA
+{
 
-namespace AlphaISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace AlphaISA
 
 #endif // __ARCH_ALPHA_PSEUDO_INST_HH__
 

diff --git a/src/arch/arm/pseudo_inst.hh b/src/arch/arm/pseudo_inst.hh
index 50c725dcf90f06e858d4d0d3ae6296a3d1d5e202..e687ed93da37fce7c703757299fa6623ea31d468 100644 (file)
--- a/src/arch/arm/pseudo_inst.hh
+++ b/src/arch/arm/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_ARM_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace ArmISA
+{
 
-namespace ArmISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace ArmISA
 
 #endif // __ARCH_ARM_PSEUDO_INST_HH__
 

diff --git a/src/arch/generic/pseudo_inst.cc b/src/arch/generic/pseudo_inst.cc
index 1c83d344fcd38bf283030b72194f5d9ddfaabe62..ec4cbfd5275ff0a2706b2b00a6710102f9c7a90b 100644 (file)
--- a/src/arch/generic/pseudo_inst.cc
+++ b/src/arch/generic/pseudo_inst.cc
@@ -36,12 +36,6 @@ class ThreadContext;
 
 using namespace GenericISA;
 
-void
-GenericISA::m5Syscall(ThreadContext *tc)
-{
-    panic("m5Syscall not implemented for current ISA");
-}
-
 void
 GenericISA::m5PageFault(ThreadContext *tc)
 {

diff --git a/src/arch/generic/pseudo_inst.hh b/src/arch/generic/pseudo_inst.hh
index 001334726b97553989745a7a90283783b19ca686..58b70fe9b2a440cb86a9fccb075f9f11a71fdc12 100644 (file)
--- a/src/arch/generic/pseudo_inst.hh
+++ b/src/arch/generic/pseudo_inst.hh
@@ -35,13 +35,6 @@ class ThreadContext;
 
 namespace GenericISA {
 
-/*
- * This function is executed when the simulation is executing the syscall
- * handler in System Emulation mode.
- */
-void
-m5Syscall(ThreadContext *tc);
-
 /*
  * This function is executed when the simulation is executing the pagefault
  * handler in System Emulation mode.

diff --git a/src/arch/mips/pseudo_inst.hh b/src/arch/mips/pseudo_inst.hh
index 3741ebc7169260ccc1c806527c877f027aafb227..1f65b344ea1aceb3d29ab2189ff4f59edea59a7b 100644 (file)
--- a/src/arch/mips/pseudo_inst.hh
+++ b/src/arch/mips/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_MIPS_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace MipsISA
+{
 
-namespace MipsISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace MipsISA
 
 #endif // __ARCH_MIPS_PSEUDO_INST_HH__
 

diff --git a/src/arch/power/pseudo_inst.hh b/src/arch/power/pseudo_inst.hh
index e1ecda23870c0ee03b1a91707cc060bb7b780cc9..99cd905282bfe13bdb9068e10b74efb6c6e5a704 100644 (file)
--- a/src/arch/power/pseudo_inst.hh
+++ b/src/arch/power/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_POWER_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace PowerISA
+{
 
-namespace PowerISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace PowerISA
 
 #endif // __ARCH_POWER_PSEUDO_INST_HH__
 

diff --git a/src/arch/riscv/pseudo_inst.hh b/src/arch/riscv/pseudo_inst.hh
index 49cceb86bf4d90145d5edf53b02f7e0734e5098b..642ffd610cc4173f4465653905570a40c9b17868 100644 (file)
--- a/src/arch/riscv/pseudo_inst.hh
+++ b/src/arch/riscv/pseudo_inst.hh
@@ -32,14 +32,12 @@
 #define __ARCH_RISCV_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace RiscvISA
+{
 
-namespace RiscvISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
 
-#endif // __ARCH_RISCV_PSEUDO_INST_HH__
+} // namespace RiscvISA
 
+#endif // __ARCH_RISCV_PSEUDO_INST_HH__

diff --git a/src/arch/sparc/pseudo_inst.hh b/src/arch/sparc/pseudo_inst.hh
index 5f9e576cc4c166b07d1e136ced242ad30303aba7..34b9758b0be7e130621cd2508ca7ae89201b95a0 100644 (file)
--- a/src/arch/sparc/pseudo_inst.hh
+++ b/src/arch/sparc/pseudo_inst.hh
@@ -32,14 +32,13 @@
 #define __ARCH_SPARC_PSEUDO_INST_HH__
 
 #include "arch/generic/pseudo_inst.hh"
-#include "base/logging.hh"
 
-class ThreadContext;
+namespace SparcISA
+{
 
-namespace SparcISA {
-    using GenericISA::m5Syscall;
-    using GenericISA::m5PageFault;
-}
+using GenericISA::m5PageFault;
+
+} // namespace SparcISA
 
 #endif // __ARCH_SPARC_PSEUDO_INST_HH__
 

diff --git a/src/arch/x86/pseudo_inst.cc b/src/arch/x86/pseudo_inst.cc
index 68bc74accefdb4bce2fe422b30ce93cfd12625a5..95d8ab8f8105286ef6effbae98ce6625dd327bc6 100644 (file)
--- a/src/arch/x86/pseudo_inst.cc
+++ b/src/arch/x86/pseudo_inst.cc
@@ -40,19 +40,6 @@ using namespace X86ISA;
 
 namespace X86ISA {
 
-/*
- * This function is executed when the simulation is executing the syscall
- * handler in System Emulation mode.
- */
-void
-m5Syscall(ThreadContext *tc)
-{
-    DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
-
-    Fault fault;
-    tc->syscall(&fault);
-}
-
 /*
  * This function is executed when the simulation is executing the pagefault
  * handler in System Emulation mode.

diff --git a/src/arch/x86/pseudo_inst.hh b/src/arch/x86/pseudo_inst.hh
index 5074d1fc3d0602b87accfd631d68c404ac5d44b7..d2a3cff7c555a828dfae6000d606864a5d7bccf0 100644 (file)
--- a/src/arch/x86/pseudo_inst.hh
+++ b/src/arch/x86/pseudo_inst.hh
@@ -33,9 +33,11 @@
 
 class ThreadContext;
 
-namespace X86ISA {
-    void m5Syscall(ThreadContext *tc);
-    void m5PageFault(ThreadContext *tc);
-}
+namespace X86ISA
+{
+
+void m5PageFault(ThreadContext *tc);
+
+} // namespace X86ISA
 
 #endif // __ARCH_X86_PSEUDO_INST_HH__

diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 92886dacb078e682677670e12a445eab5e412f82..53892b5d196c8fe6d8928074b83e2d760d995735 100644 (file)
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -586,6 +586,18 @@ switchcpu(ThreadContext *tc)
     exitSimLoop("switchcpu");
 }
 
+/*
+ * This function is executed when the simulation is executing the syscall
+ * handler in System Emulation mode.
+ */
+void
+m5Syscall(ThreadContext *tc)
+{
+    DPRINTF(PseudoInst, "PseudoInst::m5Syscall()\n");
+    Fault fault;
+    tc->syscall(&fault);
+}
+
 void
 togglesync(ThreadContext *tc)
 {

diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index d9b981f947a2e601bb0f31338a58727eb7fbd267..977ed1d39fe5c1c5ef7c89be0a1fdcc1b715641c 100644 (file)
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -88,6 +88,7 @@ void debugbreak(ThreadContext *tc);
 void switchcpu(ThreadContext *tc);
 void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
 void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
+void m5Syscall(ThreadContext *tc);
 void togglesync(ThreadContext *tc);
 
 } // namespace PseudoInst