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diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 5c1c357626ac637f3a197a57fd037ee5419100fc..1b03c6a54fbb7dc5f688a8817efbb11f97317a70 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -24,7 +24,7 @@ twin predication and twin elwidth overrides is extremely important to have to be
 
 something like:
 
-| 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 12 | 13 18 | 19 21 |
+| 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 12 | 13 18 | 19 20 |
 | ----- | --- | --- | ---- | ---- | ----- | ----- | ----- |
 | subvl | sew | dew | ptyp | psrc | pdst  | vspec | sat   |
 
@@ -33,7 +33,7 @@ something like:
 * ptyp - predication INT / CR
 * psrc / pdst - predicate mask selector and inversion
 * vspec - 3 bit src / dest scalar-vector extension
-* sat: 3 bit s/u 8/16/32
+* sat: 2 bit s/u
 
 ## twin predication, CR based.
 
@@ -51,7 +51,7 @@ With different bits being selectable (CR[0..3]) starting from the same CR makes
 
 these are of the form res = op(src1, src2, ...)
 
-| 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 18 | 19 21 |
+| 0   1 | 2 3 | 4 5 | 6    | 7  9 | 10 18 | 19 20 |
 | ----- | --- | --- | ---- | ---- | ----- | ----- |
 | subvl | sew | dew | ptyp | pred | vspec | sat   |
 
@@ -60,7 +60,7 @@ these are of the form res = op(src1, src2, ...)
 * ptyp - predication INT / CR
 * pred - predicate mask selector and inversion
 * vspec - 2/3 bit src / dest scalar-vector extension
-* sat: 3 bit s/u 8/16/32
+* sat: 2 bit s/u
 
 
 For 2 op (dest/src1/src2) the tag may be 3 bits: total 9 bits.  for 3 op (dest/src1/2/3) the vspec may be 2 bits per reg: total 8 bits.
@@ -78,15 +78,6 @@ One of the issues with vector ops is that in integer DSP ops for example in Audi
 
 If there are spare bits it would be very good to look at using some of them to specify the mode, because otherwise a SPR has to be used which will need to be set and unset.  This can get costly.
 
-Idea: 3 bits for clamping mode? similar to elwidth:
-
-* 0b000 default (no clamp)
-* 0b010 011 8 bit (sel: -128/127, us:0/255)
-* 0b100 101 16 bit
-* 0b110 111 32 bit
-
-not the same *as* elwidth.
-
 # Notes about Swizzle
 
 Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.