Add $cover cell type and SVA cover() support

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 2d58c682f2a8c9b65e42347dd8b2072d0a5a12f7..38a19a36fefb156559fcd7899be4c1a45641eee1 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -84,6 +84,7 @@ std::string AST::type2str(AstNodeType type)
        X(AST_PREFIX)
        X(AST_ASSERT)
        X(AST_ASSUME)
+       X(AST_COVER)
        X(AST_FCALL)
        X(AST_TO_BITS)
        X(AST_TO_SIGNED)

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index cd6e264e67b82c4cfafc59a8c3778494f20c3fd9..0b9116d39588e7b45d63c8c1f2d2b96fd2823c53 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -65,6 +65,7 @@ namespace AST
                AST_PREFIX,
                AST_ASSERT,
                AST_ASSUME,
+               AST_COVER,
 
                AST_FCALL,
                AST_TO_BITS,

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index db8d7409fa1324c3803171492dd86c1b365306ca..bdac4de00849dbcc9f2ad7ae8a5279de38235d11 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1336,9 +1336,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        // generate $assert cells
        case AST_ASSERT:
        case AST_ASSUME:
+       case AST_COVER:
                {
                        const char *celltype = "$assert";
                        if (type == AST_ASSUME) celltype = "$assume";
+                       if (type == AST_COVER) celltype = "$cover";
 
                        log_assert(children.size() == 2);
 

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index c1e77c6ec966949d5967bea12976cd319faf149f..eecc0413292d40e29c2a45c63d8d5be6fbc2bd42 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1400,7 +1400,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
        }
 skip_dynamic_range_lvalue_expansion:;
 
-       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && current_block != NULL)
+       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && current_block != NULL)
        {
                std::stringstream sstr;
                sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@@ -1462,7 +1462,7 @@ skip_dynamic_range_lvalue_expansion:;
                goto apply_newNode;
        }
 
-       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME) && children.size() == 1)
+       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && children.size() == 1)
        {
                children.push_back(mkconst_int(1, false, 1));
                did_something = true;

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9bf5a6c6cba530fff71adcadac56a649f8a5e9f5..f5efdea7efffce7c6a8f01530fd403fecab4bb25 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -752,8 +752,8 @@ struct VerificImporter
                        }
 
                        if (inst->Type() == PRIM_SVA_IMMEDIATE_COVER || inst->Type() == PRIM_SVA_COVER) {
-                               // Net *in = inst->GetInput();
-                               // module->addCover(NEW_ID, net_map.at(in), State::S1);
+                               Net *in = inst->GetInput();
+                               module->addCover(NEW_ID, net_map.at(in), State::S1);
                                continue;
                        }
 

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index c22fdf39c32110a249fb26815c43373bab1c8c9b..4d040e3d1efcd9b6849e2aa73dd4bc1af182ee38 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -177,6 +177,7 @@ YOSYS_NAMESPACE_END
 
 "assert"   { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
 "assume"   { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
+"cover"    { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
 "restrict" { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
 "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 "logic"    { SV_KEYWORD(TOK_REG); }

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ba47bf2d3634560d7cd8723e5a841e7bf95a3f2a..0f823a0822a8aa6e46c110529f002d69a986ced7 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -114,7 +114,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
-%token TOK_RESTRICT TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
+%token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@@ -1000,6 +1000,9 @@ assert:
        TOK_ASSUME '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
        } |
+       TOK_COVER '(' expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3));
+       } |
        TOK_RESTRICT '(' expr ')' ';' {
                if (norestrict_mode)
                        delete $3;
@@ -1014,6 +1017,9 @@ assert_property:
        TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
        } |
+       TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
+       } |
        TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
                if (norestrict_mode)
                        delete $4;

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index f0ead1e89d0d71cacb012e19718fb2fa866b78ee..04db5125e8067f4e531b09075129d8f7c3912e9f 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -116,6 +116,7 @@ struct CellTypes
 
                setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
+               setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 365bfd9f8f81d2d3457cfc78f9b1cdc9cd1981e1..978a7a53739c688b8642c8031496766c6207856e 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1026,7 +1026,7 @@ namespace {
                                return;
                        }
 
-                       if (cell->type.in("$assert", "$assume")) {
+                       if (cell->type.in("$assert", "$assume", "$cover")) {
                                port("\\A", 1);
                                port("\\EN", 1);
                                check_expected();
@@ -1819,6 +1819,14 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
        return cell;
 }
 
+RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+       RTLIL::Cell *cell = addCell(name, "$cover");
+       cell->setPort("\\A", sig_a);
+       cell->setPort("\\EN", sig_en);
+       return cell;
+}
+
 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y)
 {
        RTLIL::Cell *cell = addCell(name, "$equiv");

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8dd8fcca3aae341113ac0715bfe87f8e51e2f2d4..7a6f5717dafa6339dd44f2b446c1498fe3c2e614 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1007,6 +1007,7 @@ public:
        RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y);
        RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
        RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
+       RTLIL::Cell* addCover  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
        RTLIL::Cell* addEquiv  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
 
        RTLIL::Cell* addSr    (RTLIL::IdString name, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr, RTLIL::SigSpec sig_q, bool set_polarity = true, bool clr_polarity = true);

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index a831fdf33b00e04aed8fc20ae92ea287e8f1fb60..7686f596380a5e61c1dfefa24f148c96b2408dd9 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
 \end{fixme}
 
 \begin{fixme}

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index f1c4a1d3be23ac4ef3bdf065a6609544f0ca390c..4786aacaf6ba743338385de1655903d1b826b0d5 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
        if (cache.count(mod) == 0)
                for (auto c : mod->cells()) {
                        RTLIL::Module *m = mod->design->module(c->type);
-                       if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume"))
+                       if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover"))
                                return cache[mod] = true;
                }
        return cache[mod];

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 6600ffa25126ec72d425b3ff2e1d339abed0b6e5..65944caec9659e2acc9866bad3ed8c0e634c39f5 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -64,7 +64,7 @@ struct keep_cache_t
 
        bool query(Cell *cell)
        {
-               if (cell->type.in("$memwr", "$meminit", "$assert", "$assume"))
+               if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$cover"))
                        return true;
 
                if (cell->has_keep_attr())

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2c4db1ac6d2f24a5e2671b220cbcee7d621d07eb..d0abd3b34a80865a100283bae3f83c680f1b6596 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1305,6 +1305,14 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$cover (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$initstate (Y);
 
 output reg Y = 1;