re PR rtl-optimization/65220 (integer division in stack alignment for VLA allocation)

	PR rtl-optimization/65220
	* config/i386/i386.md (*udivmod<mode>4_pow2): New.

Co-Authored-By: Aldy Hernandez <aldyh@redhat.com>
From-SVN: r221064

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 439b42820dd9b34072c5ce2d675269e492eb371d..bae6265d6da343b87d2bd2b997ababc35844c447 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2015-02-26  Jakub Jelinek  <jakub@redhat.com>
+           Aldy Hernandez  <aldyh@redhat.com>
+
+       PR rtl-optimization/65220
+       * config/i386/i386.md (*udivmod<mode>4_pow2): New.
+
 2015-02-27  Vladimir Makarov  <vmakarov@redhat.com>
 
        PR target/65032

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2d3d07585c3dbe707a4b616cda12dd50d95d4bea..84952842b23a3751c1c9dc29d2b345b75366532f 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7331,6 +7331,32 @@
   [(set_attr "type" "multi")
    (set_attr "mode" "<MODE>")])
 
+;; Optimize division or modulo by constant power of 2, if the constant
+;; materializes only after expansion.
+(define_insn_and_split "*udivmod<mode>4_pow2"
+  [(set (match_operand:SWI48 0 "register_operand" "=r")
+       (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "0")
+                   (match_operand:SWI48 3 "const_int_operand" "n")))
+   (set (match_operand:SWI48 1 "register_operand" "=r")
+       (umod:SWI48 (match_dup 2) (match_dup 3)))
+   (clobber (reg:CC FLAGS_REG))]
+  "UINTVAL (operands[3]) - 2 < <MODE_SIZE> * BITS_PER_UNIT
+   && (UINTVAL (operands[3]) & (UINTVAL (operands[3]) - 1)) == 0"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 1) (match_dup 2))
+   (parallel [(set (match_dup 0) (lshiftrt:<MODE> (match_dup 2) (match_dup 4)))
+             (clobber (reg:CC FLAGS_REG))])
+   (parallel [(set (match_dup 1) (and:<MODE> (match_dup 1) (match_dup 5)))
+             (clobber (reg:CC FLAGS_REG))])]
+{
+  int v = exact_log2 (UINTVAL (operands[3]));
+  operands[4] = GEN_INT (v);
+  operands[5] = GEN_INT ((HOST_WIDE_INT_1U << v) - 1);
+}
+  [(set_attr "type" "multi")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "*udivmod<mode>4_noext"
   [(set (match_operand:SWIM248 0 "register_operand" "=a")
        (udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")

diff --git a/gcc/testsuite/gcc.target/i386/pr65520.c b/gcc/testsuite/gcc.target/i386/pr65520.c
new file mode 100644 (file)
index 0000000..8a62c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr65520.c
@@ -0,0 +1,20 @@
+/* PR target/65520 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int foo (void *);
+
+void
+bar (void)
+{
+  unsigned s = 128;
+  while (1)
+    {
+      unsigned b[s];
+      if (foo (b))
+       break;
+      s *= 2;
+    }
+}
+
+/* { dg-final { scan-assembler-not "div\[^\n\r]*%" } } */