tests: Make remaining switcheroo tests functional only
authorAndreas Sandberg <andreas.sandberg@arm.com>
Thu, 22 Sep 2016 09:49:08 +0000 (10:49 +0100)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Thu, 22 Sep 2016 09:49:08 +0000 (10:49 +0100)
The switcheroo tests only really serve to check functional
correctness. Checking for stat differences in them just increases the
size of reference diffs.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
39 files changed:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout [deleted file]
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY [new file with mode: 0644]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt [deleted file]
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal [deleted file]

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
deleted file mode 100644 (file)
index e12da6b..0000000
+++ /dev/null
@@ -1,1845 +0,0 @@
-[root]
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-
-[system]
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-[system.bridge]
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-[system.clk_domain]
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-[system.cpu0]
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-[system.cpu0.dcache]
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-[system.cpu0.dcache.tags]
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-[system.cpu0.dtb]
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-[system.cpu0.icache]
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-[system.cpu0.icache.tags]
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-[system.cpu0.interrupts]
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-[system.cpu0.isa]
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-[system.cpu1]
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-[system.cpu2]
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-
-[system.cpu2.branchPred]
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-[system.cpu2.dtb]
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-[system.cpu2.fuPool]
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-[system.cpu2.fuPool.FUList1.opList0]
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-[system.cpu2.fuPool.FUList2.opList0]
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-[system.cpu2.fuPool.FUList4]
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-[system.cpu2.fuPool.FUList5]
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-
-[system.cpu2.fuPool.FUList5.opList00]
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-[system.cpu2.fuPool.FUList5.opList02]
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-[system.cpu2.fuPool.FUList5.opList03]
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-[system.cpu2.fuPool.FUList5.opList04]
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-[system.cpu2.fuPool.FUList5.opList05]
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-[system.cpu2.fuPool.FUList5.opList06]
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-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
-
-[system.cpu2.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
-
-[system.cpu2.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu2.fuPool.FUList8.opList
-
-[system.cpu2.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu2.isa]
-type=AlphaISA
-eventq_index=0
-system=system
-
-[system.cpu2.itb]
-type=AlphaTLB
-eventq_index=0
-size=48
-
-[system.cpu2.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.disk0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk0.image
-
-[system.disk0.image]
-type=CowDiskImage
-children=child
-child=system.disk0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.disk2]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.disk2.image
-
-[system.disk2.image]
-type=CowDiskImage
-children=child
-child=system.disk2.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.disk2.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[27]
-mem_side=system.membus.slave[2]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[1]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.physmem.port
-slave=system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[1]
-
-[system.simple_disk]
-type=SimpleDisk
-children=disk
-disk=system.simple_disk.disk
-eventq_index=0
-system=system
-
-[system.simple_disk.disk]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img
-read_only=true
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.tsunami]
-type=Tsunami
-children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.tsunami.backdoor]
-type=AlphaBackdoor
-clk_domain=system.clk_domain
-cpu=system.cpu0
-default_p_state=UNDEFINED
-disk=system.simple_disk
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804682956800
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[24]
-
-[system.tsunami.cchip]
-type=TsunamiCChip
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8803072344064
-pio_latency=100000
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[0]
-
-[system.tsunami.ethernet]
-type=NSGigE
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=256
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=4096
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=34
-ExpansionROM=0
-HeaderType=0
-InterruptLine=30
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=52
-MinimumGrant=176
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=656
-SubClassCode=0
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=4107
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-dma_data_free=false
-dma_desc_free=false
-dma_no_allocate=true
-dma_read_delay=0
-dma_read_factor=0
-dma_write_delay=0
-dma_write_factor=0
-eventq_index=0
-hardware_address=00:90:00:00:00:01
-host=system.tsunami.pchip
-intr_delay=10000000
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-rss=false
-rx_delay=1000000
-rx_fifo_size=524288
-rx_filter=true
-rx_thread=false
-system=system
-tx_delay=1000000
-tx_fifo_size=524288
-tx_thread=false
-dma=system.iobus.slave[2]
-pio=system.iobus.master[26]
-
-[system.tsunami.fake_OROM]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8796093677568
-pio_latency=100000
-pio_size=393216
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[8]
-
-[system.tsunami.fake_ata0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848432
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.tsunami.fake_ata1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848304
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.tsunami.fake_pnp_addr]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848569
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[9]
-
-[system.tsunami.fake_pnp_read0]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848451
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.tsunami.fake_pnp_read1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848515
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.tsunami.fake_pnp_read2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848579
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[13]
-
-[system.tsunami.fake_pnp_read3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848643
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.tsunami.fake_pnp_read4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848707
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.tsunami.fake_pnp_read5]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848771
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.tsunami.fake_pnp_read6]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848835
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.tsunami.fake_pnp_read7]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848899
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[18]
-
-[system.tsunami.fake_pnp_write]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615850617
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.tsunami.fake_ppc]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848891
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[7]
-
-[system.tsunami.fake_sm_chip]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848816
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[2]
-
-[system.tsunami.fake_uart1]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848696
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[3]
-
-[system.tsunami.fake_uart2]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848936
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[4]
-
-[system.tsunami.fake_uart3]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848680
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[5]
-
-[system.tsunami.fake_uart4]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848944
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[6]
-
-[system.tsunami.fb]
-type=BadDevice
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-devicename=FrameBuffer
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848912
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.tsunami.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.disk0 system.disk2
-eventq_index=0
-host=system.tsunami.pchip
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[25]
-
-[system.tsunami.io]
-type=TsunamiIO
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-frequency=976562500
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615847936
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-tsunami=system.tsunami
-year_is_bcd=false
-pio=system.iobus.master[22]
-
-[system.tsunami.pchip]
-type=TsunamiPChip
-clk_domain=system.clk_domain
-conf_base=8804649402368
-conf_device_bits=8
-conf_size=16777216
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=8796093022208
-pci_pio_base=8804615847936
-pio_addr=8802535473152
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-tsunami=system.tsunami
-pio=system.iobus.master[1]
-
-[system.tsunami.uart]
-type=Uart8250
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=8804615848952
-pio_latency=100000
-platform=system.tsunami
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[23]
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
deleted file mode 100755 (executable)
index 9666912..0000000
+++ /dev/null
@@ -1,61 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: ClockedObject: Already in the requested power state, request ignored
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: Prefetch instructions in Alpha do not do anything
-warn: Prefetch instructions in Alpha do not do anything
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10194, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7524, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11199, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11377, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
deleted file mode 100755 (executable)
index 7e3c6c6..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39575
-command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
-
-Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
deleted file mode 100644 (file)
index 848d1d5..0000000
+++ /dev/null
@@ -1,2033 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  1.842573                       # Number of seconds simulated
-sim_ticks                                1842573194000                       # Number of ticks simulated
-final_tick                               1842573194000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 206946                       # Simulator instruction rate (inst/s)
-host_op_rate                                   206946                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5715573944                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 339016                       # Number of bytes of host memory used
-host_seconds                                   322.38                       # Real time elapsed on the host
-sim_insts                                    66714903                       # Number of instructions simulated
-sim_ops                                      66714903                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst           469248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20132864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           150208                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2123008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           298368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2617024                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             25791680                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       469248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       150208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       298368                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          917824                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7488960                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7488960                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7332                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            314576                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2347                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             33172                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4662                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             40891                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                402995                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117015                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117015                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              254670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10926493                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               81521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1152197                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              161930                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1420309                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide               521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                13997642                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         254670                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          81521                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         161930                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             498121                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4064403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4064403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4064403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             254670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10926493                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              81521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1152197                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             161930                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1420309                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide              521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18062045                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         81087                       # Number of read requests accepted
-system.physmem.writeReqs                        46731                       # Number of write requests accepted
-system.physmem.readBursts                       81087                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      46731                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5188416                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2989056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5189568                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2990784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       18                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4742                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4753                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                4837                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5252                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5163                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                5213                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5141                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                5015                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5238                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4880                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5475                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5008                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4911                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               4972                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5564                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               4905                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2655                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2725                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2864                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3189                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3009                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2838                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                3113                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2705                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3288                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2746                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3262                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2782                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2699                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2735                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               3348                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2746                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           3                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1841561317000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   81087                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  46731                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     63494                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      7529                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5570                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      4444                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        79                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2568                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     3585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     2820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     3153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     3420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     3068                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     2749                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     2819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     2602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     2211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     2272                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     2180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       90                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       58                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       48                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       89                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       62                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       35                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        7                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        21474                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      380.808047                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     217.054900                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     378.494212                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           7105     33.09%     33.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         4792     22.32%     55.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         1974      9.19%     64.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1058      4.93%     69.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          851      3.96%     73.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          468      2.18%     75.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          396      1.84%     77.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          380      1.77%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4450     20.72%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          21474                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          2032                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        39.890256                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      985.167686                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047           2030     99.90%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095            1      0.05%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::43008-45055            1      0.05%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            2032                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          2032                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        22.984252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.590209                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       23.991562                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                34      1.67%      1.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.34%      2.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11                3      0.15%      2.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               2      0.10%      2.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            1678     82.58%     84.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              43      2.12%     86.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              12      0.59%     87.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              18      0.89%     88.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             100      4.92%     93.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               2      0.10%     93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               5      0.25%     93.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               3      0.15%     93.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               1      0.05%     93.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.10%     94.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.05%     94.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.10%     94.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67               2      0.10%     94.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.05%     94.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               1      0.05%     94.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               7      0.34%     94.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               2      0.10%     94.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.10%     94.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99              82      4.04%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.05%     98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             2      0.10%     99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             2      0.10%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             1      0.05%     99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.10%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.05%     99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             2      0.10%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187             1      0.05%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.05%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223             1      0.05%     99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             7      0.34%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251             1      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            2032                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      878117500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2398161250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    405345000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10831.73                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29581.73                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.82                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.62                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.82                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.62                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         7.72                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      69338                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     36961                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14407683.71                       # Average gap between requests
-system.physmem.pageHitRate                      83.18                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   80173800                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   43646625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 312904800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                149675040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            89124122880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            35767572390                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           797968033500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             923446129035                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.080170                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   1309854007000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     45564480000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      9260985250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   82169640                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   44677875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 319433400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                152966880                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            89124122880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            35452017540                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           802163554500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             927338942715                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.741345                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   1310300112750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     45564480000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      8843530000                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dtb.fetch_hits                          0                       # ITB hits
-system.cpu0.dtb.fetch_misses                        0                       # ITB misses
-system.cpu0.dtb.fetch_acv                           0                       # ITB acv
-system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4806164                       # DTB read hits
-system.cpu0.dtb.read_misses                      6050                       # DTB read misses
-system.cpu0.dtb.read_acv                          122                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  427464                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3411517                       # DTB write hits
-system.cpu0.dtb.write_misses                      679                       # DTB write misses
-system.cpu0.dtb.write_acv                          84                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 163616                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8217681                       # DTB hits
-system.cpu0.dtb.data_misses                      6729                       # DTB misses
-system.cpu0.dtb.data_acv                          206                       # DTB access violations
-system.cpu0.dtb.data_accesses                  591080                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2722802                       # ITB hits
-system.cpu0.itb.fetch_misses                     3018                       # ITB misses
-system.cpu0.itb.fetch_acv                         101                       # ITB acv
-system.cpu0.itb.fetch_accesses                2725820                       # ITB accesses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.read_acv                            0                       # DTB read access violations
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.write_acv                           0                       # DTB write access violations
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.data_hits                           0                       # DTB hits
-system.cpu0.itb.data_misses                         0                       # DTB misses
-system.cpu0.itb.data_acv                            0                       # DTB access violations
-system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numPwrStateTransitions               6514                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         3257                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    552798033.019036                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   1352688826.519808                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         3257    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value       142000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value   3905515000                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           3257                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON    42110000457                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 1800463193543                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       928783152                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6426                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211388                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74798     40.97%     40.97% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105692     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182572                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73431     49.30%     49.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73431     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148944                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1819731049500     98.76%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               39465000      0.00%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              370305500      0.02%     98.78% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22431640000      1.22%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1842572460000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981724                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694764                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815810                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
-system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
-system.cpu0.kern.syscall::6                        42     12.88%     25.77% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.31%     26.07% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.31%     26.38% # number of syscalls executed
-system.cpu0.kern.syscall::17                       15      4.60%     30.98% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      3.07%     34.05% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      1.84%     35.89% # number of syscalls executed
-system.cpu0.kern.syscall::23                        4      1.23%     37.12% # number of syscalls executed
-system.cpu0.kern.syscall::24                        6      1.84%     38.96% # number of syscalls executed
-system.cpu0.kern.syscall::33                       11      3.37%     42.33% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.61%     42.94% # number of syscalls executed
-system.cpu0.kern.syscall::45                       54     16.56%     59.51% # number of syscalls executed
-system.cpu0.kern.syscall::47                        6      1.84%     61.35% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      3.07%     64.42% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      3.07%     67.48% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.31%     67.79% # number of syscalls executed
-system.cpu0.kern.syscall::59                        7      2.15%     69.94% # number of syscalls executed
-system.cpu0.kern.syscall::71                       54     16.56%     86.50% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      0.92%     87.42% # number of syscalls executed
-system.cpu0.kern.syscall::74                       16      4.91%     92.33% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.31%     92.64% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      0.92%     93.56% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      2.76%     96.32% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.61%     96.93% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.61%     97.55% # number of syscalls executed
-system.cpu0.kern.syscall::132                       4      1.23%     98.77% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.61%     99.39% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.61%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   326                       # number of syscalls executed
-system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 4175      2.17%      2.17% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175313     91.20%     93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.00%     96.94% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192227                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2095                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1907                      
-system.cpu0.kern.mode_good::user                 1738                      
-system.cpu0.kern.mode_good::idle                  169                      
-system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.080668                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.390979                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29732108000      1.61%      1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2585852000      0.14%      1.75% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1810254498000     98.25%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    4176                       # number of times the context was actually changed
-system.cpu0.committedInsts                   30003730                       # Number of instructions committed
-system.cpu0.committedOps                     30003730                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             27925731                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                163756                       # Number of float alu accesses
-system.cpu0.num_func_calls                     796110                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3567009                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    27925731                       # number of integer instructions
-system.cpu0.num_fp_insts                       163756                       # number of float instructions
-system.cpu0.num_int_register_reads           38434691                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          20585928                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               84641                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              86208                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8247251                       # number of memory refs
-system.cpu0.num_load_insts                    4827160                       # Number of load instructions
-system.cpu0.num_store_insts                   3420091                       # Number of store instructions
-system.cpu0.num_idle_cycles              907147772.055444                       # Number of idle cycles
-system.cpu0.num_busy_cycles              21635379.944556                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023294                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976706                       # Percentage of idle cycles
-system.cpu0.Branches                          4619076                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass              1571431      5.24%      5.24% # Class of executed instruction
-system.cpu0.op_class::IntAlu                 19496987     64.97%     70.20% # Class of executed instruction
-system.cpu0.op_class::IntMult                   31839      0.11%     70.31% # Class of executed instruction
-system.cpu0.op_class::IntDiv                        0      0.00%     70.31% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                  12846      0.04%     70.35% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     70.35% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     70.35% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     70.35% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                   1596      0.01%     70.36% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     70.36% # Class of executed instruction
-system.cpu0.op_class::MemRead                 4957504     16.52%     86.88% # Class of executed instruction
-system.cpu0.op_class::MemWrite                3423190     11.41%     98.28% # Class of executed instruction
-system.cpu0.op_class::IprAccess                515272      1.72%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                  30010665                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          1394329                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.997818                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13513290                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1394841                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.688050                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   257.899506                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    77.334042                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   176.764270                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.503710                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.151043                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.345243                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         64401814                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        64401814                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data      3982326                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1071245                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2765188                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7818759                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3123296                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       821204                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1357761                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5302261                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       113724                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19478                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        59657                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       192859                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122531                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21526                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        55288                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199345                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7105622                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1892449                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      4122949                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        13121020                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7105622                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1892449                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      4122949                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       13121020                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       711284                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        95061                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       562348                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1368693                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       164279                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        43166                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       643208                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       850653                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9354                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2180                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         7624                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        19158                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data           15                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           15                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       875563                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       138227                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1205556                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2219346                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       875563                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       138227                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1205556                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2219346                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2249916500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   8280122000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  10530038500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1722737000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  19403438202                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  21126175202                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28838500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    118651000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    147489500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       209000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       209000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3972653500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27683560202                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31656213702                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3972653500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27683560202                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31656213702                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4693610                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1166306                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      3327536                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      9187452                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3287575                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       864370                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2000969                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6152914                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123078                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21658                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        67281                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       212017                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       122531                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21526                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        55303                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199360                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      7981185                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2030676                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      5328505                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15340366                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      7981185                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2030676                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      5328505                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15340366                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.151543                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.081506                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.168998                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.148974                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049970                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.049939                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.321448                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.138252                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076001                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100656                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.113316                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.090361                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000271                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000075                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.109703                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.068069                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.226247                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.144674                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.109703                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.068069                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.226247                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.144674                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23668.134145                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14724.195694                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  7693.499200                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39909.581615                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30166.661798                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24835.244456                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13228.669725                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15562.827912                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7698.585447                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13933.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13933.333333                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28740.068872                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22963.313361                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14263.757748                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28740.068872                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22963.313361                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14263.757748                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      1005696                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         2108                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            59599                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             18                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.874377                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   117.111111                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks       837399                       # number of writebacks
-system.cpu0.dcache.writebacks::total           837399                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       293239                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       293239                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       548303                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       548303                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         2076                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         2076                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       841542                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       841542                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       841542                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       841542                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        95061                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       269109                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       364170                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        43166                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        94905                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       138071                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2180                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5548                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7728                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           15                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           15                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       138227                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       364014                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       502241                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       138227                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       364014                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       502241                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         1131                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         1713                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total         2844                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         1429                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         2015                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         3444                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         2560                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         3728                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total         6288                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2154855500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4439209000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6594064500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1679571000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3050724099                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4730295099                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26658500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     69598500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     96257000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       194000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       194000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3834426500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7489933099                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  11324359599                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3834426500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   7489933099                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  11324359599                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    248626500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    373633000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    622259500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    248626500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    373633000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total    622259500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.081506                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.080873                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039638                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.049939                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047430                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.022440                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100656                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.082460                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036450                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000271                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000075                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.068069                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.068314                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032740                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.068069                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.068314                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032740                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22668.134145                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16495.951455                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18107.105198                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38909.581615                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32145.030283                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34259.874260                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12228.669725                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12544.790916                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12455.615942                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 12933.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12933.333333                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27740.068872                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20575.947900                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22547.660583                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27740.068872                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20575.947900                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22547.660583                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219828.912467                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 218116.170461                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218797.292546                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97119.726562                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100223.444206                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98959.844148                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements           970146                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.204815                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           39666884                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           970657                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            40.866015                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10200765500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   263.084411                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    64.947265                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   183.173139                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.513837                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.126850                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.357760                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998447                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         41630359                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        41630359                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29500548                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7433858                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2732478                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       39666884                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29500548                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7433858                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2732478                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        39666884                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29500548                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7433858                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2732478                       # number of overall hits
-system.cpu0.icache.overall_hits::total       39666884                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       510117                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       127222                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       355287                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       992626                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       510117                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       127222                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       355287                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        992626                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       510117                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       127222                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       355287                       # number of overall misses
-system.cpu0.icache.overall_misses::total       992626                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1824371000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4938070984                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6762441984                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1824371000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4938070984                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6762441984                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1824371000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4938070984                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6762441984                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30010665                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7561080                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3087765                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     40659510                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30010665                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7561080                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3087765                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     40659510                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30010665                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7561080                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3087765                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     40659510                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016998                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.016826                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.115063                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.024413                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016998                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.016826                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.115063                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.024413                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016998                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.016826                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.115063                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.024413                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14340.059109                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13898.822597                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6812.678677                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14340.059109                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13898.822597                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6812.678677                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14340.059109                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13898.822597                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6812.678677                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4393                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              224                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.611607                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       970146                       # number of writebacks
-system.cpu0.icache.writebacks::total           970146                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        21777                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        21777                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        21777                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        21777                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        21777                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        21777                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127222                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       333510                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       460732                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       127222                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       333510                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       460732                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       127222                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       333510                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       460732                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1697149000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4385581487                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6082730487                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1697149000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4385581487                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6082730487                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1697149000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4385581487                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6082730487                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011331                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011331                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.016826                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.108010                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011331                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13202.318239                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13202.318239                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13340.059109                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13149.775080                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13202.318239                       # average overall mshr miss latency
-system.cpu1.dtb.fetch_hits                          0                       # ITB hits
-system.cpu1.dtb.fetch_misses                        0                       # ITB misses
-system.cpu1.dtb.fetch_acv                           0                       # ITB acv
-system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1185765                       # DTB read hits
-system.cpu1.dtb.read_misses                      1350                       # DTB read misses
-system.cpu1.dtb.read_acv                           34                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  142577                       # DTB read accesses
-system.cpu1.dtb.write_hits                     886140                       # DTB write hits
-system.cpu1.dtb.write_misses                      164                       # DTB write misses
-system.cpu1.dtb.write_acv                          19                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  58302                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2071905                       # DTB hits
-system.cpu1.dtb.data_misses                      1514                       # DTB misses
-system.cpu1.dtb.data_acv                           53                       # DTB access violations
-system.cpu1.dtb.data_accesses                  200879                       # DTB accesses
-system.cpu1.itb.fetch_hits                     858318                       # ITB hits
-system.cpu1.itb.fetch_misses                      678                       # ITB misses
-system.cpu1.itb.fetch_acv                          29                       # ITB acv
-system.cpu1.itb.fetch_accesses                 858996                       # ITB accesses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.read_acv                            0                       # DTB read access violations
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.write_acv                           0                       # DTB write access violations
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.data_hits                           0                       # DTB hits
-system.cpu1.itb.data_misses                         0                       # DTB misses
-system.cpu1.itb.data_acv                            0                       # DTB access violations
-system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numPwrStateTransitions               2295                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         1148                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    1552918826.219512                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   1902969233.500840                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         1148    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value       123500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value   6633070500                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           1148                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON    59822381500                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 1782750812500                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       953371043                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
-system.cpu1.kern.mode_switch::kernel                0                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                  0                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                  0                      
-system.cpu1.kern.mode_good::user                    0                      
-system.cpu1.kern.mode_good::idle                    0                      
-system.cpu1.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu1.committedInsts                    7559512                       # Number of instructions committed
-system.cpu1.committedOps                      7559512                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7024268                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 44783                       # Number of float alu accesses
-system.cpu1.num_func_calls                     206891                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts       914000                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7024268                       # number of integer instructions
-system.cpu1.num_fp_insts                        44783                       # number of float instructions
-system.cpu1.num_int_register_reads            9773567                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5124259                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24150                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24568                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2078876                       # number of memory refs
-system.cpu1.num_load_insts                    1190479                       # Number of load instructions
-system.cpu1.num_store_insts                    888397                       # Number of store instructions
-system.cpu1.num_idle_cycles              923345266.952757                       # Number of idle cycles
-system.cpu1.num_busy_cycles              30025776.047243                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031494                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968506                       # Percentage of idle cycles
-system.cpu1.Branches                          1187005                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass               406253      5.37%      5.37% # Class of executed instruction
-system.cpu1.op_class::IntAlu                  4898849     64.79%     70.16% # Class of executed instruction
-system.cpu1.op_class::IntMult                    8443      0.11%     70.27% # Class of executed instruction
-system.cpu1.op_class::IntDiv                        0      0.00%     70.27% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                   5163      0.07%     70.34% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     70.34% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     70.34% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     70.34% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                    816      0.01%     70.35% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     70.35% # Class of executed instruction
-system.cpu1.op_class::MemRead                 1219110     16.12%     86.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite                 889613     11.77%     98.24% # Class of executed instruction
-system.cpu1.op_class::IprAccess                132832      1.76%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                   7561079                       # Class of executed instruction
-system.cpu2.branchPred.lookups               10182069                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          9237326                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           193435                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             7648921                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                5487936                       # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            71.747845                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 365631                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             14350                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups        1844704                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits            187088                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses         1657616                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted        85690                       # Number of mispredicted indirect branches.
-system.cpu2.dtb.fetch_hits                          0                       # ITB hits
-system.cpu2.dtb.fetch_misses                        0                       # ITB misses
-system.cpu2.dtb.fetch_acv                           0                       # ITB acv
-system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3799673                       # DTB read hits
-system.cpu2.dtb.read_misses                     14845                       # DTB read misses
-system.cpu2.dtb.read_acv                          160                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  231351                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2187859                       # DTB write hits
-system.cpu2.dtb.write_misses                     3782                       # DTB write misses
-system.cpu2.dtb.write_acv                         156                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  85049                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5987532                       # DTB hits
-system.cpu2.dtb.data_misses                     18627                       # DTB misses
-system.cpu2.dtb.data_acv                          316                       # DTB access violations
-system.cpu2.dtb.data_accesses                  316400                       # DTB accesses
-system.cpu2.itb.fetch_hits                     533981                       # ITB hits
-system.cpu2.itb.fetch_misses                     2772                       # ITB misses
-system.cpu2.itb.fetch_acv                         207                       # ITB acv
-system.cpu2.itb.fetch_accesses                 536753                       # ITB accesses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.read_acv                            0                       # DTB read access violations
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.write_acv                           0                       # DTB write access violations
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.data_hits                           0                       # DTB hits
-system.cpu2.itb.data_misses                         0                       # DTB misses
-system.cpu2.itb.data_acv                            0                       # DTB access violations
-system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numPwrStateTransitions               3110                       # Number of power state transitions
-system.cpu2.pwrStateClkGateDist::samples         1555                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::mean    290577901.929260                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::stdev   445615554.555058                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1000-5e+10         1555    100.00%    100.00% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::min_value        35500                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::total           1555                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateResidencyTicks::ON   1390724556500                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::CLK_GATED 451848637500                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                        30294700                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9331724                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      40046932                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   10182069                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6040655                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     18950980                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 546368                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.MiscStallCycles               10813                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1967                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        55421                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        90541                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          526                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3087771                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               132437                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          28714918                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.394639                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.444168                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                19847963     69.12%     69.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  338255      1.18%     70.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  516605      1.80%     72.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 4056347     14.13%     86.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  883774      3.08%     89.30% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  213492      0.74%     90.05% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  260077      0.91%     90.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  443832      1.55%     92.50% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 2154573      7.50%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            28714918                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.336101                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.321912                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 7553623                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             12980509                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  7101757                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               570685                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                262482                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              224592                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                11278                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36245198                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                35745                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                262482                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 7856240                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                4908054                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5914164                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  7349808                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              2178317                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35245227                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                60989                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                402200                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 73644                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               1098810                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands           23726835                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             43551141                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        43490937                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            56291                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             20541823                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 3185012                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            542390                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         75158                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3906024                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3910206                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2331407                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           534571                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          330323                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32351146                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             700049                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 31671278                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            26658                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        3899534                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1737148                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        505950                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     28714918                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.102956                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.635713                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           17343310     60.40%     60.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            2798035      9.74%     70.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1407296      4.90%     75.04% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            4809954     16.75%     91.79% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            1078748      3.76%     95.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             629909      2.19%     97.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             420699      1.47%     99.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             175678      0.61%     99.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              51289      0.18%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       28714918                       # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  83963     19.65%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     19.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                211212     49.43%     69.08% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               132122     30.92%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             2449      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             25130857     79.35%     79.36% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               21000      0.07%     79.42% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     79.42% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd              20519      0.06%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1224      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     79.49% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3970834     12.54%     92.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2221095      7.01%     99.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            303300      0.96%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              31671278                       # Type of FU issued
-system.cpu2.iq.rate                          1.045440                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     427297                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.013492                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          92249666                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         36829058                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     30874313                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             261763                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            128201                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       120289                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              31956268                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 139858                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          223032                       # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       835467                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1428                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         6657                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       271687                       # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4727                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       223048                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                262482                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                4297358                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               190047                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           34535423                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            71039                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3910206                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2331407                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            624892                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 12907                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents               136174                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          6657                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         75410                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       204692                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              280102                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             31389945                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3824957                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           281333                       # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1484228                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     6022953                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 6845679                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2197996                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.036153                       # Inst execution rate
-system.cpu2.iew.wb_sent                      31070665                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     30994602                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 17781356                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 21603769                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.023103                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.823067                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts        4096171                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         194099                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           251035                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     28008857                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.084369                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.866736                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     18128303     64.72%     64.72% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2274965      8.12%     72.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1151627      4.11%     76.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      4494039     16.05%     93.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       560514      2.00%     95.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       204888      0.73%     95.74% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       167574      0.60%     96.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       175902      0.63%     96.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       851045      3.04%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     28008857                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            30371950                       # Number of instructions committed
-system.cpu2.commit.committedOps              30371950                       # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       5134459                       # Number of memory references committed
-system.cpu2.commit.loads                      3074739                       # Number of loads committed
-system.cpu2.commit.membars                      68371                       # Number of memory barriers committed
-system.cpu2.commit.branches                   6541536                       # Number of branches committed
-system.cpu2.commit.fp_insts                    115785                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 28855389                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              240551                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass      1222737      4.03%      4.03% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu        23599707     77.70%     81.73% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          20441      0.07%     81.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv               0      0.00%     81.80% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd         20074      0.07%     81.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     81.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     81.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     81.86% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv          1224      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     81.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        3143110     10.35%     92.21% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2061357      6.79%     99.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess       303300      1.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total         30371950                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events               851045                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                    61550290                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   69643370                       # The number of ROB writes
-system.cpu2.timesIdled                         166665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1579782                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1747467532                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   29151661                       # Number of Instructions Simulated
-system.cpu2.committedOps                     29151661                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.039210                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.039210                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.962269                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.962269                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                41082611                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               21995152                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    71087                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   74140                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                4380582                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                272883                       # number of misc regfile writes
-system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
-system.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
-system.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
-system.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
-system.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
-system.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
-system.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
-system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
-system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
-system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.iobus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                 7317                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7317                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51363                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51363                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5194                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1006                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          756                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18256                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33910                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  117360                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20776                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2717                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio          952                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total        45576                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  2707184                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2361000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy               133500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer22.occupancy               56000                       # Layer occupancy (ticks)
-system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             5888500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             2490000                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer27.occupancy            89817179                       # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9132000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17450000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.262350                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1693898501000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.262350                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078897                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078897                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
-system.iocache.tags.data_accesses              375525                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
-system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
-system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide      9479963                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total      9479963                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::tsunami.ide   2017910216                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2017910216                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   2027390179                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   2027390179                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   2027390179                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   2027390179                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54797.473988                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 54797.473988                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48563.491914                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 48563.491914                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 48589.339221                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 48589.339221                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 48589.339221                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 48589.339221                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           41512                       # number of writebacks
-system.iocache.writebacks::total                41512                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide           69                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::tsunami.ide        17264                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        17264                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        17333                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        17333                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        17333                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        17333                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      6029963                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total      6029963                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide   1153715348                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1153715348                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   1159745311                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1159745311                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   1159745311                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1159745311                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide     0.415479                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.415479                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide     0.415410                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.415410                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide     0.415410                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.415410                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87390.768116                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 87390.768116                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66827.812095                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66827.812095                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66909.670051                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 66909.670051                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66909.670051                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 66909.670051                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                   337759                       # number of replacements
-system.l2c.tags.tagsinuse                65519.967313                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4324806                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   403281                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    10.724051                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks     245.396014                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2334.791555                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    32190.823829                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      573.204668                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     8853.828657                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2257.129240                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data    19064.793350                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.003744                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.035626                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.491193                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008746                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.135099                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.034441                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.290906                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.999755                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          518                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          698                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5242                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        59064                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 38232018                       # Number of tag accesses
-system.l2c.tags.data_accesses                38232018                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.l2c.WritebackDirty_hits::writebacks       837399                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total          837399                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       969843                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          969843                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data              10                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              12                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  24                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data            15                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                15                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            90234                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            25592                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            71010                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               186836                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        502765                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        124874                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        328795                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            956434                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       479827                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data        81593                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       257548                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total           818968                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.inst              502765                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              570061                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              124874                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              107185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              328795                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              328558                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1962238                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             502765                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             570061                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             124874                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             107185                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             328795                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             328558                       # number of overall hits
-system.l2c.overall_hits::total                1962238                       # number of overall hits
-system.l2c.UpgradeReq_misses::cpu2.data             5                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                 5                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          74035                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          17572                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          23971                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115578                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7332                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         2347                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         4662                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           14341                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       240811                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        15648                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        17016                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         273475                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.inst              7332                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            314846                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2347                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             33220                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              4662                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             40987                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                403394                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst             7332                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           314846                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2347                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            33220                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             4662                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            40987                       # number of overall misses
-system.l2c.overall_misses::total               403394                       # number of overall misses
-system.l2c.UpgradeReq_miss_latency::cpu2.data       302500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       302500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1345702000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2144147000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3489849000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    193415000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    390013000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total    583428000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   1177247500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   1285023500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   2462271000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    193415000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2522949500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    390013000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3429170500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6535548000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    193415000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2522949500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    390013000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3429170500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6535548000                       # number of overall miss cycles
-system.l2c.WritebackDirty_accesses::writebacks       837399                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total       837399                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       969843                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       969843                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           10                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data            2                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              29                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data           15                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            15                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       164269                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        43164                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        94981                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302414                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       510097                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       127221                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       333457                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total        970775                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       720638                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data        97241                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data       274564                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1092443                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          510097                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          884907                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          127221                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          140405                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          333457                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          369545                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2365632                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         510097                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         884907                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         127221                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         140405                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         333457                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         369545                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2365632                       # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.294118                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.172414                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.450694                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.407099                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.252377                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382185                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.014374                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.018448                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.013981                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.014773                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.334164                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.160920                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.061975                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.250333                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014374                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.355796                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.018448                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.236601                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.013981                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.110912                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.170523                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014374                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.355796                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.018448                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.236601                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.013981                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.110912                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.170523                       # miss rate for overall accesses
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data        60500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total        60500                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76582.176189                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 89447.540778                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 30194.751596                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82409.458884                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83657.872158                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 40682.518653                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 75233.096881                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 75518.541373                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total  9003.642015                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82409.458884                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 75946.703793                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 83657.872158                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 83664.832752                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 16201.401112                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82409.458884                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 75946.703793                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83657.872158                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 83664.832752                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 16201.401112                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               75503                       # number of writebacks
-system.l2c.writebacks::total                    75503                       # number of writebacks
-system.l2c.UpgradeReq_mshr_misses::cpu2.data            5                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        17572                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        23971                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         41543                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         2347                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         4662                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total         7009                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        15648                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        17016                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        32664                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2347                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        33220                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4662                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        40987                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            81216                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2347                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        33220                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4662                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        40987                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           81216                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         1131                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         1713                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total         2844                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         1429                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         2015                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         3444                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         2560                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data         3728                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total         6288                       # number of overall MSHR uncacheable misses
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       252500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       252500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1169982000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1904437000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3074419000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    169945000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    343393000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    513338000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   1020767500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   1116825500                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   2137593000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    169945000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   2190749500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    343393000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   3021262500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5725350000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    169945000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   2190749500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    343393000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   3021262500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5725350000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    234482500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    352216500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    586699000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    234482500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    352216500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total    586699000                       # number of overall MSHR uncacheable cycles
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.294118                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.172414                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407099                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.252377                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.137371                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007220                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.160920                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.061975                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.029900                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.236601                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.110912                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034332                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018448                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.236601                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.013981                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.110912                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034332                       # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        50500                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        50500                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66582.176189                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79447.540778                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 74005.704932                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73239.834499                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65233.096881                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65633.844617                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65441.862601                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65946.703793                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73712.701588                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70495.345745                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72409.458884                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65946.703793                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73657.872158                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73712.701588                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70495.345745                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207323.165340                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205613.835377                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206293.600563                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91594.726562                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94478.674893                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 93304.548346                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        823847                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       379580                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests          408                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq                7144                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295118                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9811                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9811                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       117015                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           261705                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              133                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              97                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            115450                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           115450                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        287989                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           15                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        24288                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        33910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1143669                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           30                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1177609                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       107817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       107817                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1285426                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave        45576                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     30634176                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     30679752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2664384                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      2664384                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                33344136                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              152                       # Total snoops (count)
-system.membus.snoopTraffic                       9536                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples            742383                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001299                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.036012                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  741419     99.87%     99.87% # Request fanout histogram
-system.membus.snoop_fanout::1                     964      0.13%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total              742383                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            10929000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           389109129                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               19500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          434990750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy             365537                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests      4730225                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2364683                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1647                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1041                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1041                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq               7144                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2070475                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              9811                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             9811                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty       866906                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       970146                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict          608698                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              29                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            15                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             44                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           302414                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          302414                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        970849                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1092499                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError           15                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq           40                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2911790                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      4218095                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7129885                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    124220224                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    142912456                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              267132680                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          338659                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                   4850432                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples          4115169                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.000990                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.031456                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                4111093     99.90%     99.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                   4076      0.10%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            4115169                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         1824758000                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy            98963                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         691417859                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy         769604277                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
-system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
-system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
-system.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
-system.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
-system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
-system.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
-system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
-system.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
-system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
-system.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
-system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
-system.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
-system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
-system.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
-system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
-system.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
-system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
-system.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
-system.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
-system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
-system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
-system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1842573194000                       # Cumulative time (in ticks) in various power states
-system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
-system.cpu2.kern.mode_switch::kernel                0                       # number of protection mode switches
-system.cpu2.kern.mode_switch::user                  0                       # number of protection mode switches
-system.cpu2.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu2.kern.mode_good::kernel                  0                      
-system.cpu2.kern.mode_good::user                    0                      
-system.cpu2.kern.mode_good::idle                    0                      
-system.cpu2.kern.mode_switch_good::kernel          nan                       # fraction of useful protection mode switches
-system.cpu2.kern.mode_switch_good::user           nan                       # fraction of useful protection mode switches
-system.cpu2.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu2.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
-system.cpu2.kern.mode_ticks::kernel                 0                       # number of ticks spent at the given mode
-system.cpu2.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
-system.cpu2.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
-system.cpu2.kern.swap_context                       0                       # number of times the context was actually changed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal
deleted file mode 100644 (file)
index 8a879f5..0000000
+++ /dev/null
@@ -1,108 +0,0 @@
-M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
-\rGot Configuration 623
-\rmemsize 8000000 pages 4000 
-\rFirst free page after ROM 0xFFFFFC0000018000
-\rHWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
-\rkstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
-\rCPU Clock at 2000 MHz IntrClockFrequency=1024 
-\rBooting with 1 processor(s) 
-\rKSP: 0x20043FE8 PTBR 0x20
-\rConsole Callback at 0x0, fixup at 0x0, crb offset: 0x510
-\rMemory cluster 0 [0 - 392]
-\rMemory cluster 1 [392 - 15992]
-\rInitalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 
-\rConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8
-\runix_boot_mem ends at FFFFFC0000076000 
-\rk_argc = 0 
-\rjumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
-\rCallbackFixup 0 18000, t7=FFFFFC000070C000
-\rLinux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
-\rBooting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
-\rMajor Options: SMP LEGACY_START VERBOSE_MCHECK 
-\rCommand line: root=/dev/hda1 console=ttyS0
-\rmemcluster 0, usage 1, start        0, end      392
-\rmemcluster 1, usage 0, start      392, end    16384
-\rfreeing pages 1069:16384
-\rreserving pages 1069:1070
-\r4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles
-\rSMP: 1 CPUs probed -- cpu_present_mask = 1
-\rBuilt 1 zonelists
-\rKernel command line: root=/dev/hda1 console=ttyS0
-\rPID hash table entries: 1024 (order: 10, 32768 bytes)
-\rUsing epoch = 1900
-\rConsole: colour dummy device 80x25
-\rDentry cache hash table entries: 32768 (order: 5, 262144 bytes)
-\rInode-cache hash table entries: 16384 (order: 4, 131072 bytes)
-\rMemory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
-\rMount-cache hash table entries: 512
-\rSMP mode deactivated.
-\rBrought up 1 CPUs
-\rSMP: Total of 1 processors activated (4002.20 BogoMIPS).
-\rNET: Registered protocol family 16
-\rEISA bus registered
-\rpci: enabling save/restore of SRM state
-\rSCSI subsystem initialized
-\rsrm_env: version 0.0.5 loaded successfully
-\rInstalling knfsd (copyright (C) 1996 okir@monad.swb.de).
-\rInitializing Cryptographic API
-\rrtc: Standard PC (1900) epoch (1900) detected
-\rReal Time Clock Driver v1.12
-\rSerial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled
-\rttyS0 at I/O 0x3f8 (irq = 4) is a 8250
-\rio scheduler noop registered
-\rio scheduler anticipatory registered
-\rio scheduler deadline registered
-\rio scheduler cfq registered
-\rloop: loaded (max 8 devices)
-\rnbd: registered device at major 43
-\rns83820.c: National Semiconductor DP83820 10/100/1000 driver.
-\rPCI: Setting latency timer of device 0000:00:01.0 to 64
-\reth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
-\reth0: enabling optical transceiver
-\reth0: using 64 bit addressing.
-\reth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
-\rtun: Universal TUN/TAP device driver, 1.6
-\rtun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
-\rUniform Multi-Platform E-IDE driver Revision: 7.00alpha2
-\ride: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
-\rPIIX4: IDE controller at PCI slot 0000:00:00.0
-\rPIIX4: chipset revision 0
-\rPIIX4: 100% native mode on irq 31
-\rPCI: Setting latency timer of device 0000:00:00.0 to 64
-\r    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
-\r    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
-\rhda: M5 IDE Disk, ATA DISK drive
-\rhdb: M5 IDE Disk, ATA DISK drive
-\ride0 at 0x8410-0x8417,0x8422 on irq 31
-\rhda: max request size: 128KiB
-\rhda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
-\rhda: cache flushes not supported
-\r hda: hda1
-\rhdb: max request size: 128KiB
-\rhdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)
-\rhdb: cache flushes not supported
-\r hdb: unknown partition table
-\rmice: PS/2 mouse device common for all mice
-\rNET: Registered protocol family 2
-\rIP route cache hash table entries: 4096 (order: 2, 32768 bytes)
-\rTCP established hash table entries: 16384 (order: 5, 262144 bytes)
-\rTCP bind hash table entries: 16384 (order: 5, 262144 bytes)
-\rTCP: Hash tables configured (established 16384 bind 16384)
-\rTCP reno registered
-\rip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack
-\rip_tables: (C) 2000-2002 Netfilter core team
-\rarp_tables: (C) 2002 David S. Miller
-\rTCP bic registered
-\rInitializing IPsec netlink socket
-\rNET: Registered protocol family 1
-\rNET: Registered protocol family 17
-\rNET: Registered protocol family 15
-\rBridge firewalling registered
-\r802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
-\rAll bugs added by David S. Miller <davem@redhat.com>
-\rVFS: Mounted root (ext2 filesystem) readonly.
-\rFreeing unused kernel memory: 224k freed
-\r\rinit started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary\r
-mounting filesystems...\r
-EXT2-fs warning: checktime reached, running e2fsck is recommended
-\rloading script...\r
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY
deleted file mode 100644 (file)
index e69de29..0000000
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY
deleted file mode 100644 (file)
index e69de29..0000000
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/config.ini
deleted file mode 100644 (file)
index 80aff26..0000000
+++ /dev/null
@@ -1,1743 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dstage2_mmu dtb isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=2147483648:2415919103
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simerr
deleted file mode 100755 (executable)
index 273d7bc..0000000
+++ /dev/null
@@ -1,597 +0,0 @@
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: ClockedObject: Already in the requested power state, request ignored
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/simout
deleted file mode 100755 (executable)
index 65569f1..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:22
-gem5 executing on e108600-lin, pid 23081
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
deleted file mode 100644 (file)
index 2d1d5d1..0000000
+++ /dev/null
@@ -1,1221 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                 51.111167                       # Number of seconds simulated
-sim_ticks                                51111167268500                       # Number of ticks simulated
-final_tick                               51111167268500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 933162                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1096667                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            48559439795                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 681072                       # Number of bytes of host memory used
-host_seconds                                  1052.55                       # Real time elapsed on the host
-sim_insts                                   982198023                       # Number of instructions simulated
-sim_ops                                    1154295627                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       206336                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       188224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3278004                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         38031624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       207616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       185152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2205440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         36882368                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        436800                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             81621564                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3278004                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2205440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5483444                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    103278592                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         103299172                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         3224                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2941                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             91626                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            594257                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         3244                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2893                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             34460                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            576287                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6825                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1315757                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1613728                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1616301                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          4037                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3683                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               64135                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              744096                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          4062                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          3623                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               43150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              721611                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8546                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1596942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          64135                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          43150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             107285                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           2020666                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                403                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2021069                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           2020666                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         4037                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3683                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              64135                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             744499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         4062                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         3623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              43150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             721611                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8546                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3618010                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   145515                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               145515                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples       145515                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         145515    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       145515                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K       108307     85.67%     85.67% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        18122     14.33%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       126429                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       145515                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       145515                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       126429                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       126429                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       271944                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    91812952                       # DTB read hits
-system.cpu0.dtb.read_misses                    108269                       # DTB read misses
-system.cpu0.dtb.write_hits                   84016904                       # DTB write hits
-system.cpu0.dtb.write_misses                    37246                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51122                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              25430                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   56668                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4782                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    10953                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                91921221                       # DTB read accesses
-system.cpu0.dtb.write_accesses               84054150                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        175829856                       # DTB hits
-system.cpu0.dtb.misses                         145515                       # DTB misses
-system.cpu0.dtb.accesses                    175975371                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    70816                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                70816                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        70816                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          70816    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        70816                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        62041     96.03%     96.03% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2564      3.97%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        64605                       # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        70816                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        70816                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        64605                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        64605                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       135421                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   492374883                       # ITB inst hits
-system.cpu0.itb.inst_misses                     70816                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51122                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              25430                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    574                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40442                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               492445699                       # ITB inst accesses
-system.cpu0.itb.hits                        492374883                       # DTB hits
-system.cpu0.itb.misses                          70816                       # DTB misses
-system.cpu0.itb.accesses                    492445699                       # DTB accesses
-system.cpu0.numPwrStateTransitions              16972                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         8486                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    5850237301.708461                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   113494821184.972778                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3706     43.67%     43.67% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         4716     55.57%     99.25% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.26% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.53%     99.79% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            5      0.06%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           12      0.14%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 3977575161560                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           8486                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   1466053526202                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 49645113742298                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                     98039867564                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16775                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  492156218                       # Number of instructions committed
-system.cpu0.committedOps                    578106768                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            529626923                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                450865                       # Number of float alu accesses
-system.cpu0.num_func_calls                   28493046                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     76041586                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   529626923                       # number of integer instructions
-system.cpu0.num_fp_insts                       450865                       # number of float instructions
-system.cpu0.num_int_register_reads          782885196                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         420741799                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              732662                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             369512                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           132705210                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          132383544                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    175953589                       # number of memory refs
-system.cpu0.num_load_insts                   91907608                       # Number of load instructions
-system.cpu0.num_store_insts                  84045981                       # Number of store instructions
-system.cpu0.num_idle_cycles              96932341935.251450                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1107525628.748547                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.011297                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.988703                       # Percentage of idle cycles
-system.cpu0.Branches                        110098917                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                401201785     69.36%     69.36% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1174308      0.20%     69.56% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49945      0.01%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             53536      0.01%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.58% # Class of executed instruction
-system.cpu0.op_class::MemRead                91907608     15.89%     85.47% # Class of executed instruction
-system.cpu0.op_class::MemWrite               84045981     14.53%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 578433163                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements         11606055                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999719                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          339854312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         11606567                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            29.281209                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   263.642169                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   248.357550                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.514926                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.485073                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1417450148                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1417450148                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     85600060                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     85509890                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      171109950                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     79551757                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     79538240                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     159089997                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       209327                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       214988                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       424315                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       144230                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       192053                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       336283                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2149020                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      2154529                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      4303549                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2274909                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2280735                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4555644                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    165296047                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    165240183                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       330536230                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    165505374                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    165455171                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      330960545                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      3016323                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2986728                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      6003051                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1286923                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1264627                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2551550                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       788168                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       797714                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1585882                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       761557                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       485215                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1246772                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       126793                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       127105                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       253898                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      5064803                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4736570                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       9801373                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5852971                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5534284                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     11387255                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     88616383                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     88496618                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    177113001                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     80838680                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     80802867                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    161641547                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       997495                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data      1012702                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      2010197                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       905787                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       677268                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1583055                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2275813                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2281634                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4557447                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2274909                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2280736                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4555645                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    170360850                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    169976753                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    340337603                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    171358345                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    170989455                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    342347800                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.034038                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033750                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033894                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015920                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.015651                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015785                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.790147                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.787709                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.788919                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.840768                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.716430                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.787573                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.055713                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.055708                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.055711                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029730                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.027866                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028799                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.034156                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032366                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.033262                       # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      8918956                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8918956                       # number of writebacks
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         14265255                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.984599                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          968523793                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         14265767                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.891463                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       6061932500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   268.597080                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   243.387519                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.524604                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.475366                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999970                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          184                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          239                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        997055337                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       997055337                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    485300804                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    483222989                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      968523793                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    485300804                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    483222989                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       968523793                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    485300804                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    483222989                       # number of overall hits
-system.cpu0.icache.overall_hits::total      968523793                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      7138684                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      7127088                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     14265772                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      7138684                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      7127088                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      14265772                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      7138684                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      7127088                       # number of overall misses
-system.cpu0.icache.overall_misses::total     14265772                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    492439488                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    490350077                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    982789565                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    492439488                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    490350077                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    982789565                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    492439488                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    490350077                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    982789565                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014497                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014535                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014516                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014497                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014535                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014516                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014497                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014535                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014516                       # miss rate for overall accesses
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     14265255                       # number of writebacks
-system.cpu0.icache.writebacks::total         14265255                       # number of writebacks
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   143141                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               143141                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples       143141                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0         143141    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       143141                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walksPending::samples   1000001000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1000001000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   1000001000                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K       106696     85.47%     85.47% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        18135     14.53%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       124831                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       143141                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       143141                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       124831                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       124831                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       267972                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    91711544                       # DTB read hits
-system.cpu1.dtb.read_misses                    106091                       # DTB read misses
-system.cpu1.dtb.write_hits                   83754683                       # DTB write hits
-system.cpu1.dtb.write_misses                    37050                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51111                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              24341                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   56242                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4763                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10698                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                91817635                       # DTB read accesses
-system.cpu1.dtb.write_accesses               83791733                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        175466227                       # DTB hits
-system.cpu1.dtb.misses                         143141                       # DTB misses
-system.cpu1.dtb.accesses                    175609368                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    69344                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                69344                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples        69344                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          69344    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        69344                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        60893     96.02%     96.02% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         2524      3.98%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        63417                       # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        69344                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        69344                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        63417                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        63417                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       132761                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   490286660                       # ITB inst hits
-system.cpu1.itb.inst_misses                     69344                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51111                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              24341                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    565                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   40468                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               490356004                       # ITB inst accesses
-system.cpu1.itb.hits                        490286660                       # DTB hits
-system.cpu1.itb.misses                          69344                       # DTB misses
-system.cpu1.itb.accesses                    490356004                       # DTB accesses
-system.cpu1.numPwrStateTransitions              16542                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         8271                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    6033690194.397533                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   129465330065.337860                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3733     45.13%     45.13% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         4474     54.09%     99.23% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            2      0.02%     99.25% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            4      0.05%     99.30% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           44      0.53%     99.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11            3      0.04%     99.88% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 5966367222968                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           8271                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   1206515670638                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 49904651597862                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                     97462078889                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  490041805                       # Number of instructions committed
-system.cpu1.committedOps                    576188859                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            528250212                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                430484                       # Number of float alu accesses
-system.cpu1.num_func_calls                   28340797                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     75581054                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   528250212                       # number of integer instructions
-system.cpu1.num_fp_insts                       430484                       # number of float instructions
-system.cpu1.num_int_register_reads          777868472                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         419771352                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              687105                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             379048                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           131312247                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          131056135                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    175584466                       # number of memory refs
-system.cpu1.num_load_insts                   91803674                       # Number of load instructions
-system.cpu1.num_store_insts                  83780792                       # Number of store instructions
-system.cpu1.num_idle_cycles              96359431608.339264                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1102647280.660740                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.011314                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.988686                       # Percentage of idle cycles
-system.cpu1.Branches                        109433272                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                399627658     69.32%     69.32% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1180080      0.20%     69.52% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    50598      0.01%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             54286      0.01%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
-system.cpu1.op_class::MemRead                91803674     15.92%     85.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite               83780792     14.53%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 576497131                       # Class of executed instruction
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40242                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40242                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136515                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136515                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47598                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122480                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230954                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353514                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47618                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155610                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334248                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7491944                       # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115459                       # number of replacements
-system.iocache.tags.tagsinuse               10.407111                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115475                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13082113307009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.554597                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.852514                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.222162                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.428282                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.650444                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039650                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039650                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8813                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8850                       # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115477                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115517                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115477                       # number of overall misses
-system.iocache.overall_misses::total           115517                       # number of overall misses
-system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8813                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8850                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115477                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115517                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115477                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115517                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106631                       # number of writebacks
-system.iocache.writebacks::total               106631                       # number of writebacks
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1725813                       # number of replacements
-system.l2c.tags.tagsinuse                65403.901917                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   49468109                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1788889                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    27.652978                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    9615.108088                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   224.707200                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   268.802991                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3426.785629                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    22887.229719                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   209.300949                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   228.038258                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2648.603044                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    25895.326039                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.146715                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003429                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004102                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.052289                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.349231                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003194                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003480                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.040414                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.395131                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997984                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          371                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62705                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          371                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          110                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1444                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5122                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55700                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005661                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.956802                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                423190040                       # Number of tag accesses
-system.l2c.tags.data_accesses               423190040                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       265559                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       135827                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       262154                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       132135                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 795675                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8918956                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8918956                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     14263678                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        14263678                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data           15680                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           15013                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               30693                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           852174                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           837196                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1689370                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       7090159                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       7092615                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          14182774                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3753733                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3744979                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          7498712                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       340283                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       354274                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           694557                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        265559                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        135827                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             7090159                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4605907                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        262154                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        132135                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             7092615                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4582175                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24166531                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       265559                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       135827                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            7090159                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4605907                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       262154                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       132135                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            7092615                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4582175                       # number of overall hits
-system.l2c.overall_hits::total               24166531                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         3224                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2941                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         3244                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2893                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                12302                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1907                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1973                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3880                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         417162                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         410445                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             827607                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        48525                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        34473                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           82998                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       177551                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       166568                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         344119                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       421274                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       130941                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         552215                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         3224                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2941                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             48525                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            594713                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         3244                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2893                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             34473                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            577013                       # number of demand (read+write) misses
-system.l2c.demand_misses::total               1267026                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         3224                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2941                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            48525                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           594713                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         3244                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2893                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            34473                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           577013                       # number of overall misses
-system.l2c.overall_misses::total              1267026                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       268783                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       138768                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       265398                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       135028                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             807977                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      8918956                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      8918956                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     14263678                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     14263678                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        17587                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        16986                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           34573                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1269336                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1247641                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2516977                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      7138684                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      7127088                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      14265772                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      3931284                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data      3911547                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      7842831                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       761557                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       485215                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1246772                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       268783                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       138768                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         7138684                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         5200620                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       265398                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       135028                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         7127088                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         5159188                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25433557                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       268783                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       138768                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        7138684                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        5200620                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       265398                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       135028                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        7127088                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        5159188                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25433557                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015226                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.108432                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.116154                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.112226                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.328646                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.328977                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.328810                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006797                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.004837                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005818                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045164                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.042584                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043877                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.553175                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.269862                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.442916                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006797                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.114354                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004837                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.111842                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.049817                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.011995                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.021194                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006797                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.114354                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.012223                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.021425                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004837                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.111842                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.049817                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1507097                       # number of writebacks
-system.l2c.writebacks::total                  1507097                       # number of writebacks
-system.membus.snoop_filter.tot_requests       3778676                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1875347                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         2861                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               76679                       # Transaction distribution
-system.membus.trans_dist::ReadResp             524948                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33606                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33606                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1613728                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           226309                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4447                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4448                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            827050                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           827050                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        448269                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        658872                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       658872                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122480                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6654                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5462200                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      5591392                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       346493                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5937885                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155610                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13308                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    177701344                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    177870394                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7390784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7390784                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               185261178                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           3888961                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.009406                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.096529                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3852380     99.06%     99.06% # Request fanout histogram
-system.membus.snoop_fanout::1                   36581      0.94%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             3888961                       # Request fanout histogram
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
-system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
-system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
-system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
-system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
-system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     52388021                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26515676                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1744                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2694                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2694                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            1320370                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23428973                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33606                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33606                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      8918956                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     14265255                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2687099                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           34573                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          34574                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2516977                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2516977                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      14265772                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7842831                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1246772                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1246772                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     42883049                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35022683                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       830232                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1657150                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              80393114                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1826158228                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1234030566                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      3320928                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      6628600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3070138322                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1762508                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  96494720                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         54893925                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.011221                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.105334                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               54277951     98.88%     98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 615974      1.12%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           54893925                       # Request fanout histogram
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/system.terminal
deleted file mode 100644 (file)
index e001022..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-[    0.000000] Initializing cgroup subsys cpu\r
-[    0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[    0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[    0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[    0.000000] Memory limited to 256MB\r
-[    0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[    0.000000] On node 0 totalpages: 65536\r
-[    0.000000]   DMA zone: 896 pages used for memmap\r
-[    0.000000]   DMA zone: 0 pages reserved\r
-[    0.000000]   DMA zone: 65536 pages, LIFO batch:15\r
-[    0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[    0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 64640\r
-[    0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[    0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[    0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[    0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[    0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[    0.000000] Virtual kernel memory layout:\r
-[    0.000000]     vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000   (245759 MB)\r
-[    0.000000]     vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000   (     3 MB)\r
-[    0.000000]     modules : 0xffffffbffc000000 - 0xffffffc000000000   (    64 MB)\r
-[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc010000000   (   256 MB)\r
-[    0.000000]       .init : 0xffffffc000692000 - 0xffffffc0006c6200   (   209 kB)\r
-[    0.000000]       .text : 0xffffffc000080000 - 0xffffffc0006914e4   (  6214 kB)\r
-[    0.000000]       .data : 0xffffffc0006c7000 - 0xffffffc0007141e0   (   309 kB)\r
-[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[    0.000000] Preemptible hierarchical RCU implementation.\r
-[    0.000000]         RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[    0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[    0.000013] Console: colour dummy device 80x25\r
-[    0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[    0.000015] pid_max: default: 32768 minimum: 301\r
-[    0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000066] hw perfevents: no hardware support available\r
-[    1.060049] CPU1: failed to come online\r
-[    2.080098] CPU2: failed to come online\r
-[    3.100148] CPU3: failed to come online\r
-[    3.100150] Brought up 1 CPUs\r
-[    3.100151] SMP: Total of 1 processors activated.\r
-[    3.100177] devtmpfs: initialized\r
-[    3.100579] atomic64_test: passed\r
-[    3.100603] regulator-dummy: no parameters\r
-[    3.100844] NET: Registered protocol family 16\r
-[    3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[    3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[    3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[    3.100981] Serial: AMBA PL011 UART driver\r
-[    3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[    3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[    3.101160] console [ttyAMA0] enabled\r
-[    3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[    3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[    3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[    3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[    3.130356] 3V3: 3300 mV \r
-[    3.130377] vgaarb: loaded\r
-[    3.130406] SCSI subsystem initialized\r
-[    3.130425] libata version 3.00 loaded.\r
-[    3.130450] usbcore: registered new interface driver usbfs\r
-[    3.130457] usbcore: registered new interface driver hub\r
-[    3.130471] usbcore: registered new device driver usb\r
-[    3.130482] pps_core: LinuxPPS API ver. 1 registered\r
-[    3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[    3.130487] PTP clock support registered\r
-[    3.130559] Switched to clocksource arch_sys_counter\r
-[    3.131204] NET: Registered protocol family 2\r
-[    3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[    3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[    3.131259] TCP: Hash tables configured (established 2048 bind 2048)\r
-[    3.131263] TCP: reno registered\r
-[    3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131281] NET: Registered protocol family 1\r
-[    3.131311] RPC: Registered named UNIX socket transport module.\r
-[    3.131311] RPC: Registered udp transport module.\r
-[    3.131312] RPC: Registered tcp transport module.\r
-[    3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[    3.131315] PCI: CLS 0 bytes, default 64\r
-[    3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[    3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[    3.132687] fuse init (API version 7.23)\r
-[    3.132738] msgmni has been set to 469\r
-[    3.133992] io scheduler noop registered\r
-[    3.134025] io scheduler cfq registered (default)\r
-[    3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[    3.134298] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
-[    3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[    3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[    3.134302] pci_bus 0000:00: scanning bus\r
-[    3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[    3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[    3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[    3.134328] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
-[    3.134330] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
-[    3.134331] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
-[    3.134333] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
-[    3.134335] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
-[    3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.134354] pci_bus 0000:00: fixups for bus\r
-[    3.134355] pci_bus 0000:00: bus scan returning with max=00\r
-[    3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[    3.134362] pci 0000:00:00.0: fixup irq: got 33\r
-[    3.134363] pci 0000:00:00.0: assigning IRQ 33\r
-[    3.134366] pci 0000:00:01.0: fixup irq: got 34\r
-[    3.134367] pci 0000:00:01.0: assigning IRQ 34\r
-[    3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[    3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[    3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[    3.134374] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
-[    3.134376] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
-[    3.134378] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
-[    3.134379] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
-[    3.134381] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
-[    3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[    3.134813] ata_piix 0000:00:01.0: version 2.13\r
-[    3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[    3.134820] ata_piix 0000:00:01.0: enabling bus mastering\r
-[    3.135009] scsi0 : ata_piix\r
-[    3.135063] scsi1 : ata_piix\r
-[    3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[    3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[    3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[    3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[    3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[    3.135150] e1000 0000:00:00.0: enabling bus mastering\r
-[    3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[    3.290566] ata1.00: 2096640 sectors, multi 0: LBA \r
-[    3.290572] ata1.00: configured for UDMA/33\r
-[    3.290589] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
-[    3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[    3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[    3.290672] sd 0:0:0:0: [sda] Write Protect is off\r
-[    3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[    3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[    3.290733]  sda: sda1\r
-[    3.290795] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[    3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[    3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[    3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[    3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[    3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[    3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[    3.410886] usbcore: registered new interface driver usb-storage\r
-[    3.410912] mousedev: PS/2 mouse device common for all mice\r
-[    3.411009] usbcore: registered new interface driver usbhid\r
-[    3.411010] usbhid: USB HID core driver\r
-[    3.411025] TCP: cubic registered\r
-[    3.411026] NET: Registered protocol family 17\r
-\0[    3.411204] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[    3.411214] devtmpfs: mounted\r
-[    3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[    3.446950] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[    3.532262] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[    3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/config.ini
deleted file mode 100644 (file)
index 0608b34..0000000
+++ /dev/null
@@ -1,2973 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=atomic
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dstage2_mmu dtb isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-workload=
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu2]
-type=MinorCPU
-children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer
-branchPred=system.cpu2.branchPred
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-decodeCycleInput=true
-decodeInputBufferSize=3
-decodeInputWidth=2
-decodeToExecuteForwardDelay=1
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu2.dstage2_mmu
-dtb=system.cpu2.dtb
-enableIdling=true
-eventq_index=0
-executeAllowEarlyMemoryIssue=true
-executeBranchDelay=1
-executeCommitLimit=2
-executeCycleInput=true
-executeFuncUnits=system.cpu2.executeFuncUnits
-executeInputBufferSize=7
-executeInputWidth=2
-executeIssueLimit=2
-executeLSQMaxStoreBufferStoresPerCycle=2
-executeLSQRequestsQueueSize=1
-executeLSQStoreBufferSize=5
-executeLSQTransfersQueueSize=2
-executeMaxAccessesInMemory=2
-executeMemoryCommitLimit=1
-executeMemoryIssueLimit=1
-executeMemoryWidth=0
-executeSetTraceTimeOnCommit=true
-executeSetTraceTimeOnIssue=false
-fetch1FetchLimit=1
-fetch1LineSnapWidth=0
-fetch1LineWidth=0
-fetch1ToFetch2BackwardDelay=1
-fetch1ToFetch2ForwardDelay=1
-fetch2CycleInput=true
-fetch2InputBufferSize=2
-fetch2ToDecodeForwardDelay=1
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu2.isa
-istage2_mmu=system.cpu2.istage2_mmu
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=true
-system=system
-threadPolicy=RoundRobin
-tracer=system.cpu2.tracer
-workload=
-
-[system.cpu2.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu2.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu2.dtb
-
-[system.cpu2.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu2.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu2.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu2.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu2.dtb.walker
-
-[system.cpu2.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu2.executeFuncUnits]
-type=MinorFUPool
-children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
-eventq_index=0
-funcUnits=system.cpu2.executeFuncUnits.funcUnits0 system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2 system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4 system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6
-
-[system.cpu2.executeFuncUnits.funcUnits0]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses
-opLat=3
-timings=system.cpu2.executeFuncUnits.funcUnits0.timings
-
-[system.cpu2.executeFuncUnits.funcUnits0.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses
-
-[system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu2.executeFuncUnits.funcUnits0.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu2.executeFuncUnits.funcUnits1]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses
-opLat=3
-timings=system.cpu2.executeFuncUnits.funcUnits1.timings
-
-[system.cpu2.executeFuncUnits.funcUnits1.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses
-
-[system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntAlu
-
-[system.cpu2.executeFuncUnits.funcUnits1.timings]
-type=MinorFUTiming
-children=opClasses
-description=Int
-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses
-srcRegsRelativeLats=2
-suppress=false
-
-[system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu2.executeFuncUnits.funcUnits2]
-type=MinorFU
-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses
-opLat=3
-timings=system.cpu2.executeFuncUnits.funcUnits2.timings
-
-[system.cpu2.executeFuncUnits.funcUnits2.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses
-
-[system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntMult
-
-[system.cpu2.executeFuncUnits.funcUnits2.timings]
-type=MinorFUTiming
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-eventq_index=0
-extraAssumedLat=0
-extraCommitLat=0
-extraCommitLatExpr=Null
-mask=0
-match=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses
-srcRegsRelativeLats=0
-suppress=false
-
-[system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses]
-type=MinorOpClassSet
-eventq_index=0
-opClasses=
-
-[system.cpu2.executeFuncUnits.funcUnits3]
-type=MinorFU
-children=opClasses
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=9
-opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses
-opLat=9
-timings=
-
-[system.cpu2.executeFuncUnits.funcUnits3.opClasses]
-type=MinorOpClassSet
-children=opClasses
-eventq_index=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses
-
-[system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses]
-type=MinorOpClass
-eventq_index=0
-opClass=IntDiv
-
-[system.cpu2.executeFuncUnits.funcUnits4]
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-children=opClasses timings
-cantForwardFromFUIndices=
-eventq_index=0
-issueLat=1
-opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses
-opLat=6
-timings=system.cpu2.executeFuncUnits.funcUnits4.timings
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses]
-type=MinorOpClassSet
-children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25
-eventq_index=0
-opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatAdd
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCmp
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatCvt
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatMult
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04]
-type=MinorOpClass
-eventq_index=0
-opClass=FloatDiv
-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05]
-type=MinorOpClass
-eventq_index=0
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-
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16]
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-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18]
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-
-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24]
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-[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25]
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-
-[system.cpu2.executeFuncUnits.funcUnits4.timings]
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-
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-[system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses1]
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-
-[system.cpu2.executeFuncUnits.funcUnits6]
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-
-[system.cpu2.executeFuncUnits.funcUnits6.opClasses]
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-[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1]
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-
-[system.cpu2.istage2_mmu]
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-[system.cpu2.istage2_mmu.stage2_tlb]
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-
-[system.cpu2.istage2_mmu.stage2_tlb.walker]
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-
-[system.cpu2.itb]
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-[system.cpu2.itb.walker]
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-[system.cpu2.tracer]
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-[system.cpu3]
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-
-[system.cpu3.branchPred]
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-[system.cpu3.dstage2_mmu]
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-[system.cpu3.dstage2_mmu.stage2_tlb]
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-[system.cpu3.dstage2_mmu.stage2_tlb.walker]
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-[system.cpu3.dtb]
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-[system.cpu3.dtb.walker]
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-[system.cpu3.fuPool.FUList2]
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-[system.cpu3.fuPool.FUList2.opList0]
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-[system.cpu3.fuPool.FUList5.opList15]
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-[system.cpu3.fuPool.FUList6.opList]
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-[system.cpu3.fuPool.FUList7]
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-[system.cpu3.fuPool.FUList8.opList]
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-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu3.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu3.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu3.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu3.itb
-
-[system.cpu3.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu3.istage2_mmu.stage2_tlb.walker
-
-[system.cpu3.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu3.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu3.itb.walker
-
-[system.cpu3.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu3.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simerr
deleted file mode 100755 (executable)
index 0585c43..0000000
+++ /dev/null
@@ -1,1380 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9177, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9842, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6687, Bank: 0
-warn: ClockedObject: Already in the requested power state, request ignored
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6757, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11862, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6950, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7715, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9276, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9425, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7937, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9436, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7228, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9037, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11117, Bank: 3
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10309, Bank: 6
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8301, Bank: 7
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7119, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11014, Bank: 7
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6702, Bank: 6
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 3
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10919, Bank: 1
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11762, Bank: 7
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9036, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9399, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9127, Bank: 1
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10476, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 7
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6747, Bank: 6
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6514, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is not active!
-Command: 1, Timestamp: 3068, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 3098, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 3558, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 3589, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 4444, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8010, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6841, Bank: 4
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10958, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11294, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is not active!
-Command: 1, Timestamp: 2670, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7186, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8776, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6486, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10876, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9355, Bank: 1
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6828, Bank: 4
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout
deleted file mode 100755 (executable)
index 7162b26..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12238
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
deleted file mode 100644 (file)
index 7b0e2ea..0000000
+++ /dev/null
@@ -1,3398 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                 51.316276                       # Number of seconds simulated
-sim_ticks                                51316275690000                       # Number of ticks simulated
-final_tick                               51316275690000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 326587                       # Simulator instruction rate (inst/s)
-host_op_rate                                   383768                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            19561029283                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 692584                       # Number of bytes of host memory used
-host_seconds                                  2623.39                       # Real time elapsed on the host
-sim_insts                                   856765339                       # Number of instructions simulated
-sim_ops                                    1006773904                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker        86272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        86656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2383476                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         19569480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        22528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        19008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           645440                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5197376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker        31936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker        29376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst          1640192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          6901376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker        81152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker        66816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst          1624448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data         11589312                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        437504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             50412348                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2383476                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       645440                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst      1640192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst      1624448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         6293556                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     70023744                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70044324                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1348                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         1354                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             77649                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            305786                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker          352                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker          297                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             10085                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             81209                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker          499                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker          459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst             25628                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data            107834                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker         1268                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker         1044                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst             25382                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data            181083                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6836                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                828113                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1094121                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1096694                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          1681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          1689                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               46447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              381350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           439                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker           370                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               12578                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              101281                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker           572                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               31962                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              134487                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker          1581                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker          1302                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst               31656                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data              225841                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  982385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          46447                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          12578                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          31962                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst          31656                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             122642                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1364552                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1364953                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1364552                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         1681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         1689                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              46447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             381751                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          439                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker          370                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              12578                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             101281                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker          572                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              31962                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             134487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker         1581                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker         1302                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst              31656                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data             225841                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8526                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2347339                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        435200                       # Number of read requests accepted
-system.physmem.writeReqs                       483804                       # Number of write requests accepted
-system.physmem.readBursts                      435200                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     483804                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 27836736                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     16064                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  30961600                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  27852800                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               30963456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      251                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27905                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28763                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               27094                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24985                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               26681                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               30728                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26238                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               28208                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               24817                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29447                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28003                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29718                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              26417                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26875                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23221                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25849                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               29439                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               30169                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               29222                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               30308                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               30582                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               32929                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               29622                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               32397                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               29255                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               32999                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              30308                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              31541                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              29215                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              29346                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              27349                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              29094                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51315275469000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  435200                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 483804                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    339047                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     67972                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     19489                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                         2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       581                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       559                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       556                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       555                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      554                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      551                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      544                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    10688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    12645                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    21314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    23642                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    26112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    26953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    27836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    28305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    29478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    29464                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    30830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    31587                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    29857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    29451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    30076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    27393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    27014                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    26345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      508                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      402                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      313                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      249                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      207                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      218                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      176                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      145                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      118                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      133                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       80                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       45                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       59                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       275230                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      213.631363                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     134.345796                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     252.466079                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         131747     47.87%     47.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        72284     26.26%     74.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        24873      9.04%     83.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        12745      4.63%     87.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         8355      3.04%     90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         4904      1.78%     92.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4003      1.45%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2900      1.05%     95.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        13419      4.88%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         275230                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         25971                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.744908                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       10.064212                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-7              4094     15.76%     15.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8-15             5177     19.93%     35.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16-23           12484     48.07%     83.77% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24-31            2573      9.91%     93.67% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-39             911      3.51%     97.18% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40-47             410      1.58%     98.76% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-55             151      0.58%     99.34% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::56-63              87      0.33%     99.68% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-71              41      0.16%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::72-79              17      0.07%     99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::80-87              14      0.05%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::88-95               7      0.03%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-103              1      0.00%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::136-143             2      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::144-151             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::208-215             1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           25971                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         25971                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.627508                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.774611                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        9.820731                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-7                27      0.10%      0.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-15               58      0.22%      0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23           24184     93.12%     93.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31             657      2.53%     95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39             512      1.97%     97.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47             109      0.42%     98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55              61      0.23%     98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63              50      0.19%     98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71             187      0.72%     99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79              29      0.11%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87              13      0.05%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95               6      0.02%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103              4      0.02%     99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111            13      0.05%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119             7      0.03%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127             7      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135            17      0.07%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143             7      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151             5      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167             4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191             1      0.00%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215             2      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-255             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-263             3      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-279             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::312-319             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           25971                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8284996307                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16440290057                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2174745000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       19048.20                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37798.20                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.60                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.54                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.60                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.00                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.48                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317706                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    325786                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.04                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  67.34                       # Row buffer hit rate for writes
-system.physmem.avgGap                     55837923.96                       # Average gap between requests
-system.physmem.pageHitRate                      70.04                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1063034280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  578527125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1720625400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               1585448640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1176100438995                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29681595659250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34175675653290                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.640087                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   48913549174000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1693779100000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    116961174250                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1017704520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  553591500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1671906600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               1549413360                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3313031919600                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1173827506995                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29683698941250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34175350983825                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              667.631365                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   48916914851742                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1693779100000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    113597968758                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                    90923                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong                90923                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples        90923                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0          90923    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total        90923                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.489265                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0   -194140819580    -48.93%    -48.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1   590942018000    148.93%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        66800     85.03%     85.03% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        11762     14.97%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total        78562                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data        90923                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total        90923                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data        78562                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total        78562                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       169485                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    64271568                       # DTB read hits
-system.cpu0.dtb.read_misses                     68949                       # DTB read misses
-system.cpu0.dtb.write_hits                   58335276                       # DTB write hits
-system.cpu0.dtb.write_misses                    21974                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1189                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   41721                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  2805                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     7542                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                64340517                       # DTB read accesses
-system.cpu0.dtb.write_accesses               58357250                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        122606844                       # DTB hits
-system.cpu0.dtb.misses                          90923                       # DTB misses
-system.cpu0.dtb.accesses                    122697767                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    54169                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                54169                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples        54169                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          54169    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        54169                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 396801198420                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     1.489353                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0   -194175666580    -48.94%    -48.94% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   590976865000    148.94%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 396801198420                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        47334     95.01%     95.01% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2486      4.99%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        49820                       # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        54169                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        54169                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        49820                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        49820                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       103989                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   341484641                       # ITB inst hits
-system.cpu0.itb.inst_misses                     54169                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1189                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              16131                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    408                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   29832                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               341538810                       # ITB inst accesses
-system.cpu0.itb.hits                        341484641                       # DTB hits
-system.cpu0.itb.misses                          54169                       # DTB misses
-system.cpu0.itb.accesses                    341538810                       # DTB accesses
-system.cpu0.numPwrStateTransitions              12198                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         6099                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    8210231821.367437                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   209893503926.618408                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         2601     42.65%     42.65% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         3474     56.96%     99.61% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            5      0.08%     99.69% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11            4      0.07%     99.77% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.03%     99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.02%     99.82% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11            1      0.02%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows            9      0.15%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 7947193321500                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           6099                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   1242071811480                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074203878520                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       412415124                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16566                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  341336485                       # Number of instructions committed
-system.cpu0.committedOps                    401580232                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            368861574                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                359512                       # Number of float alu accesses
-system.cpu0.num_func_calls                   20525784                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     51873404                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   368861574                       # number of integer instructions
-system.cpu0.num_fp_insts                       359512                       # number of float instructions
-system.cpu0.num_int_register_reads          539079221                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         292860354                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              571011                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             323488                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            89499549                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           89284497                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    122681510                       # number of memory refs
-system.cpu0.num_load_insts                   64329809                       # Number of load instructions
-system.cpu0.num_store_insts                  58351701                       # Number of store instructions
-system.cpu0.num_idle_cycles              402393876.753300                       # Number of idle cycles
-system.cpu0.num_busy_cycles              10021247.246700                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.024299                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.975701                       # Percentage of idle cycles
-system.cpu0.Branches                         76154036                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                278201506     69.24%     69.24% # Class of executed instruction
-system.cpu0.op_class::IntMult                  848038      0.21%     69.45% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    41846      0.01%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  1      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             48432      0.01%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
-system.cpu0.op_class::MemRead                64329809     16.01%     85.48% # Class of executed instruction
-system.cpu0.op_class::MemWrite               58351701     14.52%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 401821333                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements          9787095                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999716                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          296232659                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          9787607                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.266097                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   496.142011                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     4.386995                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.164772                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data     6.305937                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.969027                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.008568                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.010087                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data     0.012316                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          173                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1255111411                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1255111411                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     60046999                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     19454301                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data     26463320                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data     46623681                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      152588301                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     55195720                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     17791665                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data     23636838                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data     39052226                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     135676449                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       163106                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        47592                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        79678                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data       112887                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       403263                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       128728                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data        43000                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data        56036                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data       102004                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       329768                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1435392                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       439802                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       587328                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data       976810                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3439332                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1527210                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       478716                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data       634274                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data      1126445                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3766645                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    115371447                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     37288966                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data     50156194                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data     85777911                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       288594518                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    115534553                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     37336558                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data     50235872                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data     85890798                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      288997781                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2061230                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       642663                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       875897                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data      3581810                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      7161600                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       820986                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       258023                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       651148                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data      3449880                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      5180037                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       513166                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       142485                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       214232                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data       325164                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1195047                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       655346                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       113890                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data       151535                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data       307504                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1228275                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        92447                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data        39128                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data        47209                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data       183438                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       362222                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data            7                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            7                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3537562                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1014576                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1678580                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data      7339194                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      13569912                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      4050728                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1157061                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1892812                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data      7664358                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     14764959                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   9992794500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  13884394000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data  52878438500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  76755627000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   6954335000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  17889776000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data  96530515223                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 121374626223                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data   1854766500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data   2567644000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data   5803246814                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  10225657314                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data    554773000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    665492500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data   2279898500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   3500164000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data       188500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       188500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  18801896000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  34341814000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 155212200537                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 208355910537                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  18801896000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  34341814000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 155212200537                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 208355910537                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     62108229                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     20096964                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data     27339217                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data     50205491                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    159749901                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     56016706                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     18049688                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data     24287986                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data     42502106                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    140856486                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       676272                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       190077                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       293910                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data       438051                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1598310                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       784074                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       156890                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data       207571                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data       409508                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1558043                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      1527839                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       478930                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       634537                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data      1160248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3801554                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1527210                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       478716                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       634274                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data      1126452                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3766652                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    118909009                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     38303542                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data     51834774                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data     93117105                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    302164430                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    119585281                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     38493619                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data     52128684                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data     93555156                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    303762740                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033188                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.031978                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.032038                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data     0.071343                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.044830                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.014656                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014295                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.026809                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data     0.081170                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.036775                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.758816                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.749617                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.728903                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data     0.742297                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.747694                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.835822                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.725923                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data     0.730039                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data     0.750911                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.788345                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060508                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081699                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.074399                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data     0.158102                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.095283                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data     0.000006                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000002                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029750                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.026488                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.032383                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data     0.078817                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.044909                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.033873                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.030059                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.036310                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data     0.081923                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.048607                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15549.042811                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15851.628673                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14763.049548                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10717.664628                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26952.384090                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27474.208628                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27980.832731                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23431.227658                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16285.595750                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16944.230706                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18872.101872                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total  8325.218143                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14178.414435                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14096.729437                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12428.714334                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9663.035376                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 26928.571429                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26928.571429                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18531.776821                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20458.848551                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21148.398658                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15354.256574                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16249.701615                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18143.277832                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20251.167878                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14111.512977                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      9947101                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         9301                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs           883316                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            261                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    11.261090                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    35.636015                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      7580739                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7580739                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data         2342                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data        38832                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data      1981448                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      2022622                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data           31                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       288487                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data      2860546                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      3149064                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data           16                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data         2230                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         2246                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         8708                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data        10679                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data       112790                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       132177                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         2373                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       327335                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data      4844224                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      5173932                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         2373                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       327335                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data      4844224                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      5173932                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       640321                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       837065                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data      1600362                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      3077748                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       257992                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       362661                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data       589334                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      1209987                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       142485                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       214116                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data       320624                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       677225                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       113890                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data       151519                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data       305274                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total       570683                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data        30420                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data        36530                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data        70648                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       137598                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data            7                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            7                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      1012203                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data      1351245                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data      2494970                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      4858418                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      1154688                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data      1565361                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data      2815594                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      5535643                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5039                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         4577                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data         4597                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14213                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4567                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4089                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data         4315                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        12971                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data         9606                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data         8666                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data         8912                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        27184                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   9316912500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data  12310511500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data  24145682500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  45773106500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   6694367500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   9409306500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data  17283283287                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  33386957287                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   2351295000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   3106665500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data   4848120000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  10306080500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data   1740876500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data   2415825500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data   5418758314                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total   9575460314                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    393499000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data    471106000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data    934011000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1798616000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data       181500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       181500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  17752156500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  24135643500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data  46847724101                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  88735524101                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  20103451500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  27242309000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data  51695844101                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  99041604601                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    916274500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    823963000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data    848646500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2588884000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    916274500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    823963000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data    848646500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2588884000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.031862                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.030618                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.031876                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.019266                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014293                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.014932                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.013866                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008590                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.749617                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.728509                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data     0.731933                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.423713                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725923                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data     0.729962                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data     0.745465                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.366282                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.063517                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.057570                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data     0.060890                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.036195                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data     0.000006                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026426                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.026068                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data     0.026794                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.016079                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.029997                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.030029                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data     0.030096                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.018224                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14550.377857                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14706.756942                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15087.637984                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14872.272356                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25947.965441                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25945.184346                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29326.804982                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27592.823135                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16502.052848                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14509.263670                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15120.889266                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.104027                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15285.595750                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15944.043321                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17750.474374                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16778.947882                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12935.535832                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12896.413906                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13220.629034                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13071.527202                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 25928.571429                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25928.571429                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17538.138595                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17861.781912                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18776.868700                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18264.283580                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17410.288753                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17403.211783                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18360.546336                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17891.617035                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181836.574717                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180022.503823                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184608.766587                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182149.018504                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95385.644389                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 95079.967690                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95225.145871                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95235.579753                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         15900081                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.975051                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          560800301                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         15900593                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            35.269144                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       9932119500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   471.881688                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     2.899404                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    30.014484                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst     7.179475                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.921644                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.005663                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.058622                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst     0.014022                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999951                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          292                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           63                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        592967136                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       592967136                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    336023230                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    108879045                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst     66719955                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst     49178071                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      560800301                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    336023230                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    108879045                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst     66719955                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst     49178071                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       560800301                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    336023230                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    108879045                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst     66719955                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst     49178071                       # number of overall hits
-system.cpu0.icache.overall_hits::total      560800301                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      5511231                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      1701578                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst      3909511                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst      5143815                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     16266135                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      5511231                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      1701578                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst      3909511                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst      5143815                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      16266135                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      5511231                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      1701578                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst      3909511                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst      5143815                       # number of overall misses
-system.cpu0.icache.overall_misses::total     16266135                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  22882569500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  52754697500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst  67452926346                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 143090193346                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  22882569500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst  52754697500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst  67452926346                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 143090193346                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  22882569500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst  52754697500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst  67452926346                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 143090193346                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    341534461                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    110580623                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst     70629466                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst     54321886                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    577066436                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    341534461                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    110580623                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst     70629466                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst     54321886                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    577066436                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    341534461                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    110580623                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst     70629466                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst     54321886                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    577066436                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016137                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015388                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.055352                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst     0.094691                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.028188                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016137                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015388                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.055352                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst     0.094691                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.028188                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016137                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015388                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.055352                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst     0.094691                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.028188                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13447.852229                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13493.937605                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13113.404418                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8796.815798                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8796.815798                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13447.852229                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13493.937605                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13113.404418                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8796.815798                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        37904                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             3068                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    12.354628                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     15900081                       # number of writebacks
-system.cpu0.icache.writebacks::total         15900081                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst       365435                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total       365435                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst       365435                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total       365435                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst       365435                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total       365435                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      1701578                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst      3909511                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst      4778380                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     10389469                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      1701578                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst      3909511                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst      4778380                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     10389469                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      1701578                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst      3909511                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst      4778380                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     10389469                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  21180991500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst  48845186500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst  59808862373                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 129835040373                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  21180991500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst  48845186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst  59808862373                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 129835040373                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  21180991500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst  48845186500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst  59808862373                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 129835040373                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.018004                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.018004                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015388                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.055352                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst     0.087964                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.018004                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12496.792702                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12447.852229                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12493.937605                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12516.556317                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12496.792702                       # average overall mshr miss latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                    31190                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong                31190                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2         4602                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        22894                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore            2                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples        31188                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0          31188    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total        31188                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples        27498                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23439.468325                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 20168.956165                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13617.892423                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535        27307     99.31%     99.31% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071          167      0.61%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607           10      0.04%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143            9      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total        27498                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples   2364440120                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.573010                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.494641                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     1009591500     42.70%     42.70% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1     1354848620     57.30%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total   2364440120                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        22894     83.26%     83.26% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M         4602     16.74%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total        27496                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data        31190                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total        31190                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        27496                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        27496                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total        58686                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    20771010                       # DTB read hits
-system.cpu1.dtb.read_misses                     23692                       # DTB read misses
-system.cpu1.dtb.write_hits                   18692480                       # DTB write hits
-system.cpu1.dtb.write_misses                     7498                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   17937                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  1005                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                     2603                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                20794702                       # DTB read accesses
-system.cpu1.dtb.write_accesses               18699978                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         39463490                       # DTB hits
-system.cpu1.dtb.misses                          31190                       # DTB misses
-system.cpu1.dtb.accesses                     39494680                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    19592                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                19592                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2          942                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        17338                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        19592                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          19592    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        19592                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        18280                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26364.633479                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 23452.518551                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 14371.838603                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        10663     58.33%     58.33% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535         7451     40.76%     99.09% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303           65      0.36%     99.45% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071           75      0.41%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            1      0.01%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           10      0.05%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375            1      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143            7      0.04%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911            1      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            3      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        18280                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        17338     94.85%     94.85% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M          942      5.15%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        18280                       # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        19592                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        19592                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        18280                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        18280                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total        37872                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   110580623                       # ITB inst hits
-system.cpu1.itb.inst_misses                     19592                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               5140                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    135                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   13235                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               110600215                       # ITB inst accesses
-system.cpu1.itb.hits                        110580623                       # DTB hits
-system.cpu1.itb.misses                          19592                       # DTB misses
-system.cpu1.itb.accesses                    110600215                       # DTB accesses
-system.cpu1.numPwrStateTransitions               6016                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         3008                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    4046290699.440825                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   205659188461.921204                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows          915     30.42%     30.42% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         2090     69.48%     99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11            1      0.03%     99.93% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.97% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows            1      0.03%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 11261531014001                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           3008                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   39145033266082                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171242423918                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                      1182100228                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  110507936                       # Number of instructions committed
-system.cpu1.committedOps                    129543713                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            119008832                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                107333                       # Number of float alu accesses
-system.cpu1.num_func_calls                    6516685                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     16787846                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   119008832                       # number of integer instructions
-system.cpu1.num_fp_insts                       107333                       # number of float instructions
-system.cpu1.num_int_register_reads          172055074                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          94356642                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              176403                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              83340                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            28608279                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           28519816                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                     39460487                       # number of memory refs
-system.cpu1.num_load_insts                   20769710                       # Number of load instructions
-system.cpu1.num_store_insts                  18690777                       # Number of store instructions
-system.cpu1.num_idle_cycles              1155308161.927193                       # Number of idle cycles
-system.cpu1.num_busy_cycles              26792066.072807                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.022665                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.977335                       # Percentage of idle cycles
-system.cpu1.Branches                         24662743                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 89857347     69.33%     69.33% # Class of executed instruction
-system.cpu1.op_class::IntMult                  277190      0.21%     69.54% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    11015      0.01%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 20      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.55% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             10320      0.01%     69.56% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.56% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.56% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.56% # Class of executed instruction
-system.cpu1.op_class::MemRead                20769710     16.02%     85.58% # Class of executed instruction
-system.cpu1.op_class::MemWrite               18690777     14.42%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 129616400                       # Class of executed instruction
-system.cpu2.branchPred.lookups               40854703                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         28349635                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect          2013069                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            29873482                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               20268490                       # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            67.847765                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                4987413                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            331344                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups        1163100                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits            806401                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses          356699                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted       146740                       # Number of mispredicted indirect branches.
-system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu2.dtb.walker.walks                    93799                       # Table walker walks requested
-system.cpu2.dtb.walker.walksLong                93799                       # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2         7024                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3        30187                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples        93799                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0          93799    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total        93799                       # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples        37211                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 23608.785037                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 20477.524093                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 12702.189700                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767        25796     69.32%     69.32% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-65535        11234     30.19%     99.51% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-98303           97      0.26%     99.77% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::98304-131071           57      0.15%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-163839            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::163840-196607           11      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-229375            2      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::229376-262143            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::294912-327679            2      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-360447            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::360448-393215            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total        37211                       # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples   2000359000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0     2000359000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total   2000359000                       # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K        30187     81.12%     81.12% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M         7024     18.88%    100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total        37211                       # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        93799                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        93799                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data        37211                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total        37211                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total       131010                       # Table walker requests started/completed, data/inst
-system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    28529245                       # DTB read hits
-system.cpu2.dtb.read_misses                     78357                       # DTB read misses
-system.cpu2.dtb.write_hits                   25227275                       # DTB write hits
-system.cpu2.dtb.write_misses                    15442                       # DTB write misses
-system.cpu2.dtb.flush_tlb                        1183                       # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                   22552                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                       83                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                  2182                       # Number of TLB faults due to prefetch
-system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                     3958                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                28607602                       # DTB read accesses
-system.cpu2.dtb.write_accesses               25242717                       # DTB write accesses
-system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         53756520                       # DTB hits
-system.cpu2.dtb.misses                          93799                       # DTB misses
-system.cpu2.dtb.accesses                     53850319                       # DTB accesses
-system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu2.itb.walker.walks                    27208                       # Table walker walks requested
-system.cpu2.itb.walker.walksLong                27208                       # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2         1843                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3        22528                       # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples        27208                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0          27208    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total        27208                       # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples        24371                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 26858.233146                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 23932.181675                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 13621.050617                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767        13667     56.08%     56.08% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535        10461     42.92%     99.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303           87      0.36%     99.36% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071          133      0.55%     99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839            3      0.01%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607           12      0.05%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375            1      0.00%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143            2      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911            3      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215            2      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total        24371                       # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples   2000327000                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0     2000327000    100.00%    100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total   2000327000                       # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K        22528     92.44%     92.44% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M         1843      7.56%    100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total        24371                       # Table walker page sizes translated
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst        27208                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total        27208                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst        24371                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total        24371                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total        51579                       # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits                    70683304                       # ITB inst hits
-system.cpu2.itb.inst_misses                     27208                       # ITB inst misses
-system.cpu2.itb.read_hits                           0                       # DTB read hits
-system.cpu2.itb.read_misses                         0                       # DTB read misses
-system.cpu2.itb.write_hits                          0                       # DTB write hits
-system.cpu2.itb.write_misses                        0                       # DTB write misses
-system.cpu2.itb.flush_tlb                        1183                       # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid               7123                       # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid                    191                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                   16893                       # Number of entries that have been flushed from TLB
-system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                    51118                       # Number of TLB faults due to permissions restrictions
-system.cpu2.itb.read_accesses                       0                       # DTB read accesses
-system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                70710512                       # ITB inst accesses
-system.cpu2.itb.hits                         70683304                       # DTB hits
-system.cpu2.itb.misses                          27208                       # DTB misses
-system.cpu2.itb.accesses                     70710512                       # DTB accesses
-system.cpu2.numPwrStateTransitions               7024                       # Number of power state transitions
-system.cpu2.pwrStateClkGateDist::samples         3512                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::mean    14368150694.236048                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::stdev   129350965742.418961                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::underflows         1152     32.80%     32.80% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1000-5e+10         2323     66.14%     98.95% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::5e+10-1e+11            6      0.17%     99.12% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11            3      0.09%     99.20% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11            2      0.06%     99.26% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11            2      0.06%     99.32% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11            2      0.06%     99.37% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11            1      0.03%     99.40% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11            1      0.03%     99.43% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11            1      0.03%     99.46% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11            1      0.03%     99.49% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::overflows           18      0.51%    100.00% # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::max_value 1988791978000                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateClkGateDist::total           3512                       # Distribution of time spent in the clock gated state
-system.cpu2.pwrStateResidencyTicks::ON   855330451843                       # Cumulative time (in ticks) in various power states
-system.cpu2.pwrStateResidencyTicks::CLK_GATED 50460945238157                       # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles                      1176516719                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.committedInsts                  147979887                       # Number of instructions committed
-system.cpu2.committedOps                    173747082                       # Number of ops (including micro ops) committed
-system.cpu2.discardedOps                     15034502                       # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends                     1577                       # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles                     5675627                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi                              7.950518                       # CPI: cycles per instruction
-system.cpu2.ipc                              0.125778                       # IPC: instructions per cycle
-system.cpu2.op_class_0::No_OpClass                  0      0.00%      0.00% # Class of committed instruction
-system.cpu2.op_class_0::IntAlu              120575025     69.40%     69.40% # Class of committed instruction
-system.cpu2.op_class_0::IntMult                357276      0.21%     69.60% # Class of committed instruction
-system.cpu2.op_class_0::IntDiv                  14709      0.01%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatAdd                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatCmp                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatCvt                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatMult                   0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatDiv                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::FloatSqrt                   0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdAdd                     0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdAddAcc                  0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdAlu                     0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdCmp                     0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdCvt                     0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdMisc                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdMult                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdMultAcc                 0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdShift                   0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdShiftAcc                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdSqrt                    0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAdd                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatAlu                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCmp                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatCvt                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatDiv                0      0.00%     69.61% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMisc           16361      0.01%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMult               0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatMultAcc            0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::SimdFloatSqrt               0      0.00%     69.62% # Class of committed instruction
-system.cpu2.op_class_0::MemRead              27648708     15.91%     85.53% # Class of committed instruction
-system.cpu2.op_class_0::MemWrite             25135003     14.47%    100.00% # Class of committed instruction
-system.cpu2.op_class_0::IprAccess                   0      0.00%    100.00% # Class of committed instruction
-system.cpu2.op_class_0::InstPrefetch                0      0.00%    100.00% # Class of committed instruction
-system.cpu2.op_class_0::total               173747082                       # Class of committed instruction
-system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.tickCycles                      278731731                       # Number of cycles that the object actually ticked
-system.cpu2.idleCycles                      897784988                       # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups               76144884                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted         50917651                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect          3425676                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups            51078726                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits               34631446                       # Number of BTB hits
-system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            67.800137                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                9824308                       # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect            106925                       # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups        2992006                       # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits           1537953                       # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses         1454053                       # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted       245625                       # Number of mispredicted indirect branches.
-system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu3.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu3.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu3.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu3.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu3.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu3.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu3.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu3.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu3.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu3.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu3.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu3.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu3.dtb.walker.walks                   512874                       # Table walker walks requested
-system.cpu3.dtb.walker.walksLong               512874                       # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2         8606                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3        51328                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore       316923                       # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples       195951                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean  2195.235033                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 13338.016362                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535       194716     99.37%     99.37% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071          870      0.44%     99.81% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607          208      0.11%     99.92% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143           62      0.03%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679           47      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215           18      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751           23      0.01%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287            5      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total       195951                       # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples       235338                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 21271.290654                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 17097.378529                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 15945.708212                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-32767       189296     80.44%     80.44% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-65535        41383     17.58%     98.02% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-98303         3580      1.52%     99.54% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::98304-131071          595      0.25%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-163839          139      0.06%     99.85% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::163840-196607          148      0.06%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-229375           80      0.03%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::229376-262143           73      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-294911           24      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-360447            5      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::360448-393215           11      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-425983            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total       235338                       # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -21468826588                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean     0.564464                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -22023506588    102.58%    102.58% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7    315278500     -1.47%    101.12% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11    105205000     -0.49%    100.63% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15     64047000     -0.30%    100.33% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19     24089000     -0.11%    100.21% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23     11371500     -0.05%    100.16% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27     12408500     -0.06%    100.10% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31     18570000     -0.09%    100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35      3540000     -0.02%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39       163500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43         7000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -21468826588                       # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K        51328     85.64%     85.64% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M         8606     14.36%    100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total        59934                       # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data       512874                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total       512874                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data        59934                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total        59934                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total       572808                       # Table walker requests started/completed, data/inst
-system.cpu3.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu3.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu3.dtb.read_hits                    59857088                       # DTB read hits
-system.cpu3.dtb.read_misses                    352696                       # DTB read misses
-system.cpu3.dtb.write_hits                   46573459                       # DTB write hits
-system.cpu3.dtb.write_misses                   160178                       # DTB write misses
-system.cpu3.dtb.flush_tlb                        1182                       # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries                   29518                       # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults                       76                       # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults                  5036                       # Number of TLB faults due to prefetch
-system.cpu3.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults                    30761                       # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses                60209784                       # DTB read accesses
-system.cpu3.dtb.write_accesses               46733637                       # DTB write accesses
-system.cpu3.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu3.dtb.hits                        106430547                       # DTB hits
-system.cpu3.dtb.misses                         512874                       # DTB misses
-system.cpu3.dtb.accesses                    106943421                       # DTB accesses
-system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu3.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu3.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu3.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu3.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu3.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu3.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu3.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu3.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu3.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu3.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu3.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu3.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu3.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu3.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu3.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu3.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu3.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu3.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.cpu3.itb.walker.walks                    59319                       # Table walker walks requested
-system.cpu3.itb.walker.walksLong                59319                       # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2         2009                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3        40532                       # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore         8154                       # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples        51165                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean  1195.836998                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev  7646.415303                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767        50755     99.20%     99.20% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535          251      0.49%     99.69% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303           94      0.18%     99.87% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071           39      0.08%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839           13      0.03%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607            9      0.02%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-360447            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total        51165                       # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples        50695                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 26787.010553                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 22469.536393                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 17840.810022                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767        30103     59.38%     59.38% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535        19510     38.49%     97.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303          511      1.01%     98.87% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071          427      0.84%     99.72% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839           38      0.07%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607           57      0.11%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375           19      0.04%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143            7      0.01%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911            8      0.02%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679            3      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447            4      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215            5      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::458752-491519            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total        50695                       # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -25766386884                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean     0.899092                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev     0.296211                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0    -2567658104      9.97%      9.97% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1   -23226705280     90.14%    100.11% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2       24531500     -0.10%    100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3        2936500     -0.01%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4         267500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5          75500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6         120000     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::7          45500     -0.00%    100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -25766386884                       # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K        40532     95.28%     95.28% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M         2009      4.72%    100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total        42541                       # Table walker page sizes translated
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst        59319                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total        59319                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst        42541                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total        42541                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total       101860                       # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits                    54449151                       # ITB inst hits
-system.cpu3.itb.inst_misses                     59319                       # ITB inst misses
-system.cpu3.itb.read_hits                           0                       # DTB read hits
-system.cpu3.itb.read_misses                         0                       # DTB read misses
-system.cpu3.itb.write_hits                          0                       # DTB write hits
-system.cpu3.itb.write_misses                        0                       # DTB write misses
-system.cpu3.itb.flush_tlb                        1182                       # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid              11696                       # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid                    295                       # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries                   22325                       # Number of entries that have been flushed from TLB
-system.cpu3.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu3.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu3.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults                   110276                       # Number of TLB faults due to permissions restrictions
-system.cpu3.itb.read_accesses                       0                       # DTB read accesses
-system.cpu3.itb.write_accesses                      0                       # DTB write accesses
-system.cpu3.itb.inst_accesses                54508470                       # ITB inst accesses
-system.cpu3.itb.hits                         54449151                       # DTB hits
-system.cpu3.itb.misses                          59319                       # DTB misses
-system.cpu3.itb.accesses                     54508470                       # DTB accesses
-system.cpu3.numPwrStateTransitions               7056                       # Number of power state transitions
-system.cpu3.pwrStateClkGateDist::samples         3528                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::mean    48263626.625000                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::stdev   1100096495.861649                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::underflows         2141     60.69%     60.69% # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::1000-5e+10         1387     39.31%    100.00% # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::max_value  36012902604                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateClkGateDist::total           3528                       # Distribution of time spent in the clock gated state
-system.cpu3.pwrStateResidencyTicks::ON   51146001615267                       # Cumulative time (in ticks) in various power states
-system.cpu3.pwrStateResidencyTicks::CLK_GATED 170274074733                       # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles                       360624311                       # number of cpu cycles simulated
-system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles         142734409                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                     337961407                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                   76144884                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches          45993707                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                    196711593                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                7739189                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles                   1372744                       # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles                5006                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles             1830                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles      2692575                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles        88196                       # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles         3852                       # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines                 54321925                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes              2128480                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes                  22518                       # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples         347479672                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.136573                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.381700                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0               264664577     76.17%     76.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                10448751      3.01%     79.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                10389657      2.99%     82.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                 7726776      2.22%     84.39% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                15569597      4.48%     88.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                 5085732      1.46%     90.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                 5566487      1.60%     91.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                 4803146      1.38%     93.32% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                23224949      6.68%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total           347479672                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.211147                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       0.937156                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles               116319092                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles            159338087                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                 61493208                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles              7257195                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles               3070348                       # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved            11216097                       # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred               810528                       # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts             368877230                       # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts              2502393                       # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles               3070348                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles               120537316                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles               11607372                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles     129961960                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                 64445904                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles             17854957                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts             360009684                       # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents                40582                       # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents                995330                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents                792465                       # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents               7726817                       # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents            2104                       # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands          342963420                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            547080576                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups       423978365                       # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups           517857                       # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps            286215822                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                56747593                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts           7972839                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts       6835897                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                 39855447                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads            58319848                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores           48888042                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads          7618365                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores         8042184                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                 341704043                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded            8022599                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                340232336                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued           497337                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined       47823760                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     30164946                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved        192380                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples    347479672                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        0.979143                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.691890                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0          216057167     62.18%     62.18% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1           53646928     15.44%     77.62% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2           24868918      7.16%     84.77% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3           17968855      5.17%     89.95% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4           13078366      3.76%     93.71% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5            9279622      2.67%     96.38% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6            6367435      1.83%     98.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7            3674225      1.06%     99.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8            2538156      0.73%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total      347479672                       # Number of insts issued each cycle
-system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                1739394     26.12%     26.12% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                 17216      0.26%     26.38% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                   1075      0.02%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%     26.40% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead               2643113     39.69%     66.09% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite              2258125     33.91%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass                5      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu            230928850     67.87%     67.87% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult              888251      0.26%     68.13% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                40201      0.01%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                204      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.15% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc         42408      0.01%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.16% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead            61160195     17.98%     86.14% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite           47172222     13.86%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total             340232336                       # Type of FU issued
-system.cpu3.iq.rate                          0.943454                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                    6658923                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.019572                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads        1034449548                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes        397601121                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses    327921647                       # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads             651056                       # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes            333937                       # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses       289983                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses             346543457                       # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses                 347797                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads         2684612                       # Number of loads that had data forwarded from stores
-system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads      9848030                       # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses        12099                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation       390855                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores      4852885                       # Number of stores squashed
-system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads      2121686                       # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked      3886704                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles               3070348                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                8044361                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles              2703635                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts          349811697                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts          1019337                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts             58319848                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts            48888042                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts           6684338                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                123262                       # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents              2534169                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents        390855                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect       1464138                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect      1603865                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts             3068003                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts            336172243                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts             59848506                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts          3553985                       # Number of squashed instructions skipped in execute
-system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        85055                       # number of nop insts executed
-system.cpu3.iew.exec_refs                   106421072                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                62316621                       # Number of branches executed
-system.cpu3.iew.exec_stores                  46572566                       # Number of stores executed
-system.cpu3.iew.exec_rate                    0.932195                       # Inst execution rate
-system.cpu3.iew.wb_sent                     329026261                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                    328211630                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                162144042                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                281134898                       # num instructions consuming a value
-system.cpu3.iew.wb_rate                      0.910121                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.576748                       # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts       47849721                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls        7830219                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts          2626302                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples    339381548                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     0.889568                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.882377                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0    230141242     67.81%     67.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1     52578609     15.49%     83.30% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2     18989562      5.60%     88.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3      8770494      2.58%     91.48% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4      6420925      1.89%     93.38% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5      3757747      1.11%     94.48% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6      3513397      1.04%     95.52% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7      2195731      0.65%     96.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8     13013841      3.83%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total    339381548                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts           256941031                       # Number of instructions committed
-system.cpu3.commit.committedOps             301902877                       # Number of ops (including micro ops) committed
-system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                      92506974                       # Number of memory references committed
-system.cpu3.commit.loads                     48471817                       # Number of loads committed
-system.cpu3.commit.membars                    2097304                       # Number of memory barriers committed
-system.cpu3.commit.branches                  57364518                       # Number of branches committed
-system.cpu3.commit.fp_insts                    278173                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                277550130                       # Number of committed integer instructions.
-system.cpu3.commit.function_calls             7627094                       # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu       208647320     69.11%     69.11% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult         682317      0.23%     69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv           29904      0.01%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd              0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu              0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp              0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt              0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt             0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv            0      0.00%     69.35% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc        36362      0.01%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.36% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead       48471817     16.06%     85.41% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite      44035157     14.59%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total        301902877                       # Class of committed instruction
-system.cpu3.commit.bw_lim_events             13013841                       # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads                   673991782                       # The number of ROB reads
-system.cpu3.rob.rob_writes                  707616779                       # The number of ROB writes
-system.cpu3.timesIdled                        2425895                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                       13144639                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                 98725614751                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                  256941031                       # Number of Instructions Simulated
-system.cpu3.committedOps                    301902877                       # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi                              1.403529                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        1.403529                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              0.712489                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        0.712489                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads               395604640                       # number of integer regfile reads
-system.cpu3.int_regfile_writes              235195836                       # number of integer regfile writes
-system.cpu3.fp_regfile_reads                   565870                       # number of floating regfile reads
-system.cpu3.fp_regfile_writes                  351196                       # number of floating regfile writes
-system.cpu3.cc_regfile_reads                 70807437                       # number of cc regfile reads
-system.cpu3.cc_regfile_writes                71493240                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads              657110629                       # number of misc regfile reads
-system.cpu3.misc_regfile_writes               7862543                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40272                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40272                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136539                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136539                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47694                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122576                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230966                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230966                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353622                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47714                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155706                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492088                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             13499000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                 5500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy                17500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy                5000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            10442000                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            21712500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           227539905                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            39848000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy            45034000                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115465                       # number of replacements
-system.iocache.tags.tagsinuse               10.425444                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115481                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13087293844009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.544651                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.880792                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.221541                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.430050                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651590                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039704                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039704                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8819                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8856                       # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115483                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115523                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115483                       # number of overall misses
-system.iocache.overall_misses::total           115523                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide     61770218                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     61770218                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide   5167926687                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   5167926687                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide   5229696905                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5229696905                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide   5229696905                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5229696905                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8819                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8856                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115483                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115523                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115483                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115523                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide  7004.220206                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total  6974.956865                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48450.523954                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 48450.523954                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 45269.746328                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 45285.426470                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 45269.746328                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           417                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   40                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    10.425000                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106631                       # number of writebacks
-system.iocache.writebacks::total               106631                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide          453                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          453                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide        43744                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        43744                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide        44197                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        44197                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide        44197                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        44197                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide     39120218                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     39120218                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   2977819124                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   2977819124                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   3016939342                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   3016939342                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   3016939342                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   3016939342                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.051366                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.051152                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.410110                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.410110                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.382582                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide     0.382714                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.382582                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86358.097130                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 86358.097130                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68073.772952                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68073.772952                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 68261.179311                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 68261.179311                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1182494                       # number of replacements
-system.l2c.tags.tagsinuse                65447.621193                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   49776356                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1245426                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    39.967333                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                395496000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   10450.326675                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   193.502647                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   222.666592                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3323.622390                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    21949.117178                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    56.686764                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker    60.274211                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      949.191230                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     6589.162943                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    69.129700                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker    76.155286                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2308.881020                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     7819.148817                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker   140.556158                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker   161.169200                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst     1712.244141                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data     9365.786241                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.159459                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.002953                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003398                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.050714                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.334917                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000865                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000920                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.014484                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.100543                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.001055                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.001162                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.035231                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.119311                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker     0.002145                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker     0.002459                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.026127                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data       0.142911                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998651                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          384                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        62548                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          384                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          328                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1131                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5605                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55378                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005859                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.954407                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                420660189                       # Number of tag accesses
-system.l2c.tags.data_accesses               420660189                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       148411                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       102905                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        50987                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker        37863                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       145669                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        53387                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker       286140                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker        98751                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 924113                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7580739                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7580739                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     15897541                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        15897541                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data           10116                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data            3190                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data            4337                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data            7288                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               24931                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu3.data             5                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 5                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           624653                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           203950                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data           287508                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data           472182                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1588293                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       5476670                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       1691493                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst       3883882                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst       4752795                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          15804840                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      2544942                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       782243                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data      1049975                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data      1919039                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6296199                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       281232                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data        93381                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu2.data       121660                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu3.data       233276                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           729549                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        148411                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        102905                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             5476670                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             3169595                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         50987                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker         37863                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             1691493                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              986193                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        145669                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         53387                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst             3883882                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data             1337483                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker        286140                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker         98751                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst             4752795                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data             2391221                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                24613445                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       148411                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       102905                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            5476670                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            3169595                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        50987                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker        37863                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            1691493                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             986193                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       145669                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        53387                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst            3883882                       # number of overall hits
-system.l2c.overall_hits::cpu2.data            1337483                       # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker       286140                       # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker        98751                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst            4752795                       # number of overall hits
-system.l2c.overall_hits::cpu3.data            2391221                       # number of overall hits
-system.l2c.overall_hits::total               24613445                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1348                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         1354                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker          352                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker          297                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker          499                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker          459                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker         1269                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.itb.walker         1055                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 6633                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1519                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           482                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           628                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data          1231                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3860                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu3.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         184700                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          50370                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          70224                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data         111495                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             416789                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        34561                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        10085                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst        25629                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst        25382                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           95657                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       121901                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data        30983                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data        37700                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data        69735                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         260319                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       374112                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data        20509                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu2.data        29859                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu3.data        71998                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         496478                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1348                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         1354                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             34561                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            306601                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker          352                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker          297                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             10085                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             81353                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker          499                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker          459                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst             25629                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data            107924                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker         1269                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.itb.walker         1055                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst             25382                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data            181230                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                779398                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1348                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         1354                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            34561                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           306601                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker          352                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker          297                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            10085                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            81353                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker          499                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker          459                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst            25629                       # number of overall misses
-system.l2c.overall_misses::cpu2.data           107924                       # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker         1269                       # number of overall misses
-system.l2c.overall_misses::cpu3.itb.walker         1055                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst            25382                       # number of overall misses
-system.l2c.overall_misses::cpu3.data           181230                       # number of overall misses
-system.l2c.overall_misses::total               779398                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker     29403500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker     26495000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker     43837500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker     40434000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker    112747500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.itb.walker     93804500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      346722000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      9065500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data     11493000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data     21540500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     42099000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu3.data        86000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total        86000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4112169500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   5777401500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data  11171660500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  21061231500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    833482500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst   2164843000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst   2195026000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   5193351500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data   2618754500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data   3195444500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data   6292724500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  12106923500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data        57000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu2.data        59000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu3.data       233000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total       349000                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker     29403500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker     26495000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    833482500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   6730924000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker     43837500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker     40434000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst   2164843000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   8972846000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.dtb.walker    112747500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.itb.walker     93804500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst   2195026000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data  17464385000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     38708228500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker     29403500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker     26495000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    833482500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   6730924000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker     43837500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker     40434000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst   2164843000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   8972846000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.dtb.walker    112747500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.itb.walker     93804500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst   2195026000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data  17464385000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    38708228500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       149759                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       104259                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        51339                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker        38160                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker       146168                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        53846                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker       287409                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker        99806                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             930746                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      7580739                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      7580739                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     15897541                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     15897541                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        11635                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         3672                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         4965                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data         8519                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           28791                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data            7                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             7                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       809353                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       254320                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data       357732                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data       583677                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2005082                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      5511231                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      1701578                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst      3909511                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst      4778177                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      15900497                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      2666843                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       813226                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data      1087675                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data      1988774                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6556518                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       655344                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       113890                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data       151519                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data       305274                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1226027                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       149759                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       104259                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         5511231                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         3476196                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        51339                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker        38160                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         1701578                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         1067546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       146168                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        53846                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst         3909511                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data         1445407                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker       287409                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker        99806                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst         4778177                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data         2572451                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            25392843                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       149759                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       104259                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        5511231                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        3476196                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        51339                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker        38160                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        1701578                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        1067546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       146168                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        53846                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst        3909511                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data        1445407                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker       287409                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker        99806                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst        4778177                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data        2572451                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           25392843                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.007127                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.130554                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.131264                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.126485                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data     0.144501                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.134070                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data     0.285714                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.285714                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.228207                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.198058                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.196303                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data     0.191022                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.207866                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.006271                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005927                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.006556                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst     0.005312                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.006016                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.045710                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.038099                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.034661                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data     0.035064                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.039704                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.570864                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.180077                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data     0.197064                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data     0.235847                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.404949                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.006271                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.088200                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005927                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.076206                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.006556                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.074667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005312                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.070450                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.030694                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.009001                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.012987                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.006271                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.088200                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.006856                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.007783                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005927                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.076206                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003414                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.008524                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.006556                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.074667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker     0.004415                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker     0.010571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005312                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.070450                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.030694                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52272.274989                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18808.091286                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 18300.955414                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 17498.375305                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 10906.476684                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data        43000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        43000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81639.259480                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82271.039815                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 100198.757792                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 50532.119370                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82645.761031                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 84468.492723                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 86479.631235                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 54291.390071                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84522.302553                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84759.801061                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 90237.678354                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 46508.028611                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     2.779268                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data     1.975954                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data     3.236201                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     0.702952                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 49664.264599                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83532.670455                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89208.754209                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82645.761031                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 82737.256155                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87850.701403                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88091.503268                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 84468.492723                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 83140.413624                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 88847.517730                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88914.218009                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 86479.631235                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 96365.861061                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 49664.264599                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks              987490                       # number of writebacks
-system.l2c.writebacks::total                   987490                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker            1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker           11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data            2                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data            3                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.dtb.walker            1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker           11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data              3                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.dtb.walker            1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker           11                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data             3                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker          352                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker          297                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker          499                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker          459                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker         1268                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.itb.walker         1044                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            3919                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          482                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          628                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data         1231                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2341                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu3.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        50370                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        70224                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data       111495                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        232089                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        10085                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst        25628                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst        25382                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        61095                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data        30983                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data        37698                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data        69732                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       138413                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data        20509                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu2.data        29859                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu3.data        71998                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       122366                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker          352                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker          297                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        10085                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        81353                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker          499                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker          459                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst        25628                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data       107922                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker         1268                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.itb.walker         1044                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst        25382                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data       181227                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           435516                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker          352                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker          297                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        10085                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        81353                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker          499                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker          459                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst        25628                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data       107922                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker         1268                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.itb.walker         1044                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst        25382                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data       181227                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          435516                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5039                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data         4577                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data         4597                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        14213                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4567                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4089                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data         4315                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        12971                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data         9606                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data         8666                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data         8912                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        27184                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    306745501                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      9150000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     11919000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data     23381500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     44450500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data        95500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        95500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3608469500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   5075161500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data  10056705012                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  18740336012                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    732632500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst   1908425001                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst   1941197018                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   4582254519                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data   2308918013                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data   2818373501                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data   5595188544                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  10722480058                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data    384451000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data    580665000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data   1458533500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total   2423649500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    732632500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   5917387513                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst   1908425001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   7893535001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst   1941197018                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data  15651893556                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  34351816090                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker     25883500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker     23525000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    732632500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   5917387513                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker     38847500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker     35844000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst   1908425001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   7893535001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker     99977501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.itb.walker     82668000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst   1941197018                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data  15651893556                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  34351816090                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    853214500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    766744000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data    791147500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   2411106000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    853214500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    766744000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data    791147500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2411106000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.004211                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.131264                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.126485                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data     0.144501                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.081310                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data     0.285714                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.285714                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.198058                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.196303                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data     0.191022                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.115750                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.003842                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.038099                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.034659                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data     0.035063                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.021111                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.180077                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data     0.197064                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data     0.235847                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.099807                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.017151                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.006856                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.007783                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005927                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.076206                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003414                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.008524                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.006555                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.074665                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker     0.004412                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker     0.010460                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.005312                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data     0.070449                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.017151                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 78271.370503                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18983.402490                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18979.299363                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.907392                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18987.825716                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data        47750                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        47750                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71639.259480                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72271.039815                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 90198.708570                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 80746.334432                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75002.119961                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74522.093180                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74761.883946                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80238.463604                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77467.290341                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18745.477595                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19446.900432                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20257.972444                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19806.559829                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72645.761031                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72737.176416                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74466.403972                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73141.111182                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76479.277362                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86366.234369                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 78876.128753                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169322.186942                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167521.083679                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172100.826626                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169640.892141                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88820.997293                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88477.267482                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 88773.283214                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 88695.776928                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       2692221                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1332095                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         2857                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               76739                       # Transaction distribution
-system.membus.trans_dist::ReadResp             448186                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33648                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33648                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1094121                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           202838                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4443                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1867                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            416227                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           416227                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        371447                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        603124                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp       437026                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122576                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6762                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3707227                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3836623                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       302374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       302374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4138997                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155706                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13524                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    113227104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    113396466                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7366016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7366016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               120762482                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              546                       # Total snoops (count)
-system.membus.snoopTraffic                      34880                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           2213347                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.016167                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.126119                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 2177563     98.38%     98.38% # Request fanout histogram
-system.membus.snoop_fanout::1                   35784      1.62%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             2213347                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            45757000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1572000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          3230054159                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2350415750                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy            2301227                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
-system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
-system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
-system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
-system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
-system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     52031861                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     26343539                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         3136                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2272                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2272                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316275690000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            1497693                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          23955179                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33648                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33648                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      8020839                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     15900080                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2311396                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           28791                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             7                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          28798                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2005082                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2005082                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      15900700                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6556911                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1231319                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1226027                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     47787527                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     29554737                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       797902                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1720271                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              79860437                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2035409428                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1033316830                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2813832                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      5963920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3077504010                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1542362                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  65849016                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         38107926                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.016628                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.127874                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               37474258     98.34%     98.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 633668      1.66%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           38107926                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        31293825988                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           519265                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       15589080685                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        7944642139                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         286385229                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         714971913                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.cpu3.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu3.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/system.terminal
deleted file mode 100644 (file)
index 60da7d5..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-[    0.000000] Initializing cgroup subsys cpu\r
-[    0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[    0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[    0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[    0.000000] Memory limited to 256MB\r
-[    0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[    0.000000] On node 0 totalpages: 65536\r
-[    0.000000]   DMA zone: 896 pages used for memmap\r
-[    0.000000]   DMA zone: 0 pages reserved\r
-[    0.000000]   DMA zone: 65536 pages, LIFO batch:15\r
-[    0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[    0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 64640\r
-[    0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[    0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[    0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[    0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[    0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[    0.000000] Virtual kernel memory layout:\r
-[    0.000000]     vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000   (245759 MB)\r
-[    0.000000]     vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000   (     3 MB)\r
-[    0.000000]     modules : 0xffffffbffc000000 - 0xffffffc000000000   (    64 MB)\r
-[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc010000000   (   256 MB)\r
-[    0.000000]       .init : 0xffffffc000692000 - 0xffffffc0006c6200   (   209 kB)\r
-[    0.000000]       .text : 0xffffffc000080000 - 0xffffffc0006914e4   (  6214 kB)\r
-[    0.000000]       .data : 0xffffffc0006c7000 - 0xffffffc0007141e0   (   309 kB)\r
-[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[    0.000000] Preemptible hierarchical RCU implementation.\r
-[    0.000000]         RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[    0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[    0.000027] Console: colour dummy device 80x25\r
-[    0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[    0.000032] pid_max: default: 32768 minimum: 301\r
-[    0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000178] hw perfevents: no hardware support available\r
-[    1.060046] CPU1: failed to come online\r
-[    2.080096] CPU2: failed to come online\r
-[    3.100147] CPU3: failed to come online\r
-[    3.100149] Brought up 1 CPUs\r
-[    3.100150] SMP: Total of 1 processors activated.\r
-[    3.100176] devtmpfs: initialized\r
-[    3.100785] atomic64_test: passed\r
-[    3.100840] regulator-dummy: no parameters\r
-[    3.101093] NET: Registered protocol family 16\r
-[    3.101177] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[    3.101181] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[    3.101220] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[    3.101221] Serial: AMBA PL011 UART driver\r
-[    3.101343] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[    3.101365] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[    3.101399] console [ttyAMA0] enabled\r
-[    3.101504] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[    3.101554] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[    3.101604] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[    3.101650] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[    3.130356] 3V3: 3300 mV \r
-[    3.130376] vgaarb: loaded\r
-[    3.130417] SCSI subsystem initialized\r
-[    3.130486] libata version 3.00 loaded.\r
-[    3.130565] usbcore: registered new interface driver usbfs\r
-[    3.130591] usbcore: registered new interface driver hub\r
-[    3.130645] usbcore: registered new device driver usb\r
-[    3.130677] pps_core: LinuxPPS API ver. 1 registered\r
-[    3.130687] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[    3.130706] PTP clock support registered\r
-[    3.130855] Switched to clocksource arch_sys_counter\r
-[    3.131768] NET: Registered protocol family 2\r
-[    3.131855] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[    3.131877] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[    3.131903] TCP: Hash tables configured (established 2048 bind 2048)\r
-[    3.131917] TCP: reno registered\r
-[    3.131924] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131935] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131962] NET: Registered protocol family 1\r
-[    3.131997] RPC: Registered named UNIX socket transport module.\r
-[    3.132007] RPC: Registered udp transport module.\r
-[    3.132015] RPC: Registered tcp transport module.\r
-[    3.132023] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[    3.132034] PCI: CLS 0 bytes, default 64\r
-[    3.132128] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[    3.132192] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[    3.133873] fuse init (API version 7.23)\r
-[    3.133951] msgmni has been set to 469\r
-[    3.135925] io scheduler noop registered\r
-[    3.135963] io scheduler cfq registered (default)\r
-[    3.136172] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[    3.136184] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
-[    3.136190] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[    3.136191] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[    3.136192] pci_bus 0000:00: scanning bus\r
-[    3.136195] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[    3.136196] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[    3.136199] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.136216] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[    3.136218] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
-[    3.136220] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
-[    3.136222] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
-[    3.136223] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
-[    3.136225] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
-[    3.136227] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.136244] pci_bus 0000:00: fixups for bus\r
-[    3.136245] pci_bus 0000:00: bus scan returning with max=00\r
-[    3.136247] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[    3.136252] pci 0000:00:00.0: fixup irq: got 33\r
-[    3.136253] pci 0000:00:00.0: assigning IRQ 33\r
-[    3.136256] pci 0000:00:01.0: fixup irq: got 34\r
-[    3.136257] pci 0000:00:01.0: assigning IRQ 34\r
-[    3.136259] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[    3.136261] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[    3.136263] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[    3.136264] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
-[    3.136266] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
-[    3.136268] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
-[    3.136270] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
-[    3.136271] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
-[    3.136760] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[    3.137008] ata_piix 0000:00:01.0: version 2.13\r
-[    3.137017] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[    3.137033] ata_piix 0000:00:01.0: enabling bus mastering\r
-[    3.137199] scsi0 : ata_piix\r
-[    3.137254] scsi1 : ata_piix\r
-[    3.137271] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[    3.137272] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[    3.137333] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[    3.137334] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[    3.137338] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[    3.137340] e1000 0000:00:00.0: enabling bus mastering\r
-[    3.290858] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[    3.290859] ata1.00: 2096640 sectors, multi 0: LBA \r
-[    3.290865] ata1.00: configured for UDMA/33\r
-[    3.290882] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
-[    3.290943] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[    3.290951] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[    3.290965] sd 0:0:0:0: [sda] Write Protect is off\r
-[    3.290967] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[    3.290973] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[    3.291027]  sda: sda1\r
-[    3.291088] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[    3.411147] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[    3.411162] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[    3.411191] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[    3.411202] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[    3.411233] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[    3.411246] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[    3.411369] usbcore: registered new interface driver usb-storage\r
-[    3.411437] mousedev: PS/2 mouse device common for all mice\r
-[    3.411617] usbcore: registered new interface driver usbhid\r
-[    3.411627] usbhid: USB HID core driver\r
-[    3.411648] TCP: cubic registered\r
-[    3.411655] NET: Registered protocol family 17\r
-\0[    3.411869] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[    3.411879] devtmpfs: mounted\r
-[    3.411887] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[    3.450103] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[    3.543155] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[    3.681074] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/config.ini
deleted file mode 100644 (file)
index b148595..0000000
+++ /dev/null
@@ -1,2571 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=DerivO3CPU
-children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu0.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu0.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-trapLatency=13
-wbWidth=8
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
-eventq_index=0
-
-[system.cpu0.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu0.fuPool.FUList0.opList
-
-[system.cpu0.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
-
-[system.cpu0.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu0.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu0.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
-
-[system.cpu0.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu0.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
-
-[system.cpu0.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu0.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu0.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu0.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList4.opList
-
-[system.cpu0.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
-
-[system.cpu0.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu0.fuPool.FUList6.opList
-
-[system.cpu0.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
-
-[system.cpu0.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu0.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu0.fuPool.FUList8.opList
-
-[system.cpu0.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=DerivO3CPU
-children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu1.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-default_p_state=UNDEFINED
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu1.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=
-isa=system.cpu1.isa
-issueToExecuteDelay=1
-issueWidth=8
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=false
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-trapLatency=13
-wbWidth=8
-workload=
-
-[system.cpu1.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-indirectHashGHR=true
-indirectHashTargets=true
-indirectPathLength=3
-indirectSets=256
-indirectTagSize=16
-indirectWays=2
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-useIndirect=true
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
-eventq_index=0
-
-[system.cpu1.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu1.fuPool.FUList0.opList
-
-[system.cpu1.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
-
-[system.cpu1.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu1.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=20
-pipelined=false
-
-[system.cpu1.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
-
-[system.cpu1.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu1.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
-
-[system.cpu1.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu1.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu1.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu1.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList4.opList
-
-[system.cpu1.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
-
-[system.cpu1.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu1.fuPool.FUList6.opList
-
-[system.cpu1.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
-
-[system.cpu1.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu1.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu1.fuPool.FUList8.opList
-
-[system.cpu1.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simerr
deleted file mode 100755 (executable)
index d1f615e..0000000
+++ /dev/null
@@ -1,469 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/simout
deleted file mode 100755 (executable)
index 6162f24..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug  1 2016 17:10:05
-gem5 started Aug  1 2016 17:10:34
-gem5 executing on e108600-lin, pid 12209
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt
deleted file mode 100644 (file)
index cbc921b..0000000
+++ /dev/null
@@ -1,2871 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                 51.317217                       # Number of seconds simulated
-sim_ticks                                51317217215000                       # Number of ticks simulated
-final_tick                               51317217215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 222365                       # Simulator instruction rate (inst/s)
-host_op_rate                                   261300                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            12534471719                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 700016                       # Number of bytes of host memory used
-host_seconds                                  4094.09                       # Real time elapsed on the host
-sim_insts                                   910382802                       # Number of instructions simulated
-sim_ops                                    1069785844                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       183360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       154432                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          3744320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         27933912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       182144                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       147072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          3576960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         29113392                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        413632                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             65449224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      3744320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      3576960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         7321280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     83967296                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          83987876                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         2865                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2413                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             58505                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            436475                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2846                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2298                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             55890                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            454902                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           6463                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1022657                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1311989                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1314562                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          3573                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          3009                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               72964                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              544338                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          3549                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               69703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              567322                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             8060                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1275385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          72964                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          69703                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             142667                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1636240                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                401                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1636641                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1636240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         3573                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         3009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              72964                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             544739                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         3549                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2866                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              69703                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             567322                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            8060                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2912027                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1022657                       # Number of read requests accepted
-system.physmem.writeReqs                      1314562                       # Number of write requests accepted
-system.physmem.readBursts                     1022657                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1314562                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 65407680                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     42368                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  83988672                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  65449224                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               83987876                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      662                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2238                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               60981                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               62566                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               61229                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               58916                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               63354                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               70912                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               62699                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               61112                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               58244                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               84348                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              65094                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              66290                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              61782                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              66140                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              59027                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              59301                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               79428                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               80879                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               81341                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               82396                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               84257                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               87543                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               80825                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               81935                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               79231                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               83962                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              83023                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              84619                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              80226                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              84960                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              78537                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              79161                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                         117                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51317216009000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1022642                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
-system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1311989                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    563394                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    302594                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    104127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     46335                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       752                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       511                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       662                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       460                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1269                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       340                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      210                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      200                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      145                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      131                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      106                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       99                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       59                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                       795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                       741                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                       737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                       732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                       726                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                       727                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                       723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                       722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                       720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                       725                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                      723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                      722                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                      720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                      716                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                      723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    21758                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    29866                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    42370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    50746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    67407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    74973                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    78027                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    83029                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    86506                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    84131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    87193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    90592                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    82439                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    80936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    81560                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    72513                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    71387                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    67468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     4671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     3626                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     2857                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                     2460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                     2209                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                     2161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                     2023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                     1772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                     1830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                     1704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                     1713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                     1782                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                     1531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                     1525                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                     1496                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                     1299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                     1289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                     1434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                     1251                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                     1191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                     1291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                     1069                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                     1091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                     1044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      852                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                      760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                      751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                      793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                      438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                      266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                      292                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       584051                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      255.792785                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     152.875634                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     294.556382                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         254148     43.51%     43.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       146795     25.13%     68.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        55909      9.57%     78.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27613      4.73%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        21352      3.66%     86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        11974      2.05%     88.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895        10495      1.80%     90.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7232      1.24%     91.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        48533      8.31%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         584051                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61706                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        16.562133                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev       65.554683                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           61699     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023            3      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61706                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61706                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        21.267348                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.511616                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       23.799712                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-15              139      0.23%      0.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31           57235     92.75%     92.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47            1751      2.84%     95.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63             438      0.71%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79             620      1.00%     97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95             435      0.70%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111            261      0.42%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127           360      0.58%     99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143           146      0.24%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159            47      0.08%     99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175            57      0.09%     99.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191            58      0.09%     99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207            16      0.03%     99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223            17      0.03%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239            19      0.03%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255            28      0.05%     99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271            17      0.03%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287            15      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351             6      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367             3      0.00%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383             5      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399             4      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415             4      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495             2      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511             1      0.00%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527             3      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::608-623             1      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::640-655             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::752-767             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::768-783             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::784-799             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::832-847             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::848-863             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::880-895             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::896-911             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61706                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    27544031458                       # Total ticks spent queuing
-system.physmem.totMemAccLat               46706437708                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   5109975000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       26951.24                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  45701.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.64                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.28                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.64                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.79                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     789656                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    960610                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                     21956528.68                       # Average gap between requests
-system.physmem.pageHitRate                      74.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2223494280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1213216125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3913798200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4267753920                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3351790802880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1231075762515                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29710436097000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34304920924920                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.487622                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49425844576094                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1713594480000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    177772818906                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2191931280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1195994250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                4057723800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               4236099120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3351790802880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1231757755830                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29709837865500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34305068172660                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.490491                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49424824907095                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1713594480000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    178797453905                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst          768                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst         1408                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total          2212                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst          768                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst         1408                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total         2176                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           12                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst           22                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             39                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           15                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           27                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               43                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           15                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           27                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           42                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           15                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           27                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              43                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups              134591179                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted         90304193                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect          5810526                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups            90589543                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits               61837798                       # Number of BTB hits
-system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            68.261519                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS               17370059                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect            190077                       # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups        5078772                       # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits           2686505                       # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses         2392267                       # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted       411015                       # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   913460                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               913460                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        17456                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94858                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore       564703                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       348757                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean  2510.769676                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 14687.468261                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535       346035     99.22%     99.22% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071         1894      0.54%     99.76% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607          459      0.13%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143          149      0.04%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679          127      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215           27      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751           61      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       348757                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       428972                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 22512.397080                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18206.266840                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 16738.101214                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       419694     97.84%     97.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071         8206      1.91%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607          548      0.13%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143          418      0.10%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           68      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           26      0.01%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            6      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       428972                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 361724793256                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     0.150757                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev     0.705483                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 360695140256     99.72%     99.72% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7    568723500      0.16%     99.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11    203544500      0.06%     99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15    117776000      0.03%     99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19     46114500      0.01%     99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23     23872000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27     26539000      0.01%     99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31     36172500      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35      6478000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39       375000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43        38000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47         6500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51        12500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55         1000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 361724793256                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        94859     84.46%     84.46% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        17456     15.54%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       112315                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       913460                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       913460                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       112315                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       112315                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total      1025775                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                   106460809                       # DTB read hits
-system.cpu0.dtb.read_misses                    623704                       # DTB read misses
-system.cpu0.dtb.write_hits                   82932208                       # DTB write hits
-system.cpu0.dtb.write_misses                   289756                       # DTB write misses
-system.cpu0.dtb.flush_tlb                        1080                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21954                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   55225                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      193                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  9182                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                    56785                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses               107084513                       # DTB read accesses
-system.cpu0.dtb.write_accesses               83221964                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        189393017                       # DTB hits
-system.cpu0.dtb.misses                         913460                       # DTB misses
-system.cpu0.dtb.accesses                    190306477                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                   102224                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong               102224                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         2961                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        69807                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore        13996                       # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples        88228                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean  1371.061341                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev  8977.114896                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767        87329     98.98%     98.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535          530      0.60%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303          216      0.24%     99.83% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071           99      0.11%     99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839           20      0.02%     99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607           15      0.02%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375            6      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911            2      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679            4      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        88228                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        86764                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 27719.480430                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 23267.563993                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 18820.928470                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        84648     97.56%     97.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071         1819      2.10%     99.66% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607          174      0.20%     99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           69      0.08%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           30      0.03%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215           20      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        86764                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 597945449536                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean     0.915932                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev     0.277880                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0    50325346976      8.42%      8.42% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1   547568596060     91.58%     99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2       46828000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3        4056500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4         391500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5          54500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6         126500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::7          49500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 597945449536                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        69807     95.93%     95.93% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         2961      4.07%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72768                       # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst       102224                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total       102224                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72768                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72768                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       174992                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                    95313688                       # ITB inst hits
-system.cpu0.itb.inst_misses                    102224                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                        1080                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21954                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    534                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   40789                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                   189995                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                95415912                       # ITB inst accesses
-system.cpu0.itb.hits                         95313688                       # DTB hits
-system.cpu0.itb.misses                         102224                       # DTB misses
-system.cpu0.itb.accesses                     95415912                       # DTB accesses
-system.cpu0.numPwrStateTransitions              16182                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         8091                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    3359442146.645409                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   64779765350.946983                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3624     44.79%     44.79% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         4450     55.00%     99.79% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.80% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            3      0.04%     99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.86% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 1988782283928                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           8091                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   24135970806492                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 27181246408508                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                       673796045                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles         248201376                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                     597842349                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                  134591179                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches          81894362                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                    386081151                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles               13278647                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                   2497741                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles               21664                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             3050                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles      4790854                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       168722                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles         2591                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                 95107499                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes              3628886                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                  39039                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples         648406203                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             1.078367                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.330450                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0               501760932     77.38%     77.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                18256203      2.82%     80.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                18220690      2.81%     83.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                13435350      2.07%     85.08% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                28609960      4.41%     89.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                 9048805      1.40%     90.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 9824320      1.52%     92.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                 8413306      1.30%     93.70% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                40836637      6.30%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total           648406203                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.199751                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.887275                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles               201305382                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles            321428647                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                106579942                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles             13809088                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               5281102                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved            19732890                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred              1377081                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts             652345167                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts              4243358                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               5281102                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles               208974593                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               22808368                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles     259762289                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                112590129                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles             38987372                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts             636948284                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                76415                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents               1870283                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents               1736148                       # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents              19269388                       # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents            3866                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands          608166873                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            978325960                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       751087221                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           834633                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps            511551111                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                96615757                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts          15505583                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts      13521940                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 76964594                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads           102747908                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores           87125063                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads         13952178                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores        14707468                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                 603971660                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded           15594199                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                604455425                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           868037                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined       82226578                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     51472860                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        368538                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples    648406203                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.932217                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.660002                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0          412086930     63.55%     63.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           99690109     15.37%     78.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2           43563237      6.72%     85.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3           31279787      4.82%     90.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4           23126821      3.57%     94.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5           16303260      2.51%     96.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6           11232229      1.73%     98.28% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7            6608117      1.02%     99.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8            4515713      0.70%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total      648406203                       # Number of insts issued each cycle
-system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                3047764     25.70%     25.70% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                 24416      0.21%     25.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                   3438      0.03%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.94% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4792960     40.42%     66.35% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite              3990225     33.65%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass               49      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu            410215443     67.87%     67.87% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult             1414052      0.23%     68.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                66288      0.01%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                164      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc         69960      0.01%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead           108687129     17.98%     86.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite           84002340     13.90%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total             604455425                       # Type of FU issued
-system.cpu0.iq.rate                          0.897090                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                   11858803                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.019619                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads        1868979076                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes        701958936                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses    582265082                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads            1064817                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            542988                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       473036                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses             615746479                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 567700                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads         4852034                       # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads     16874429                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses        20604                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation       721236                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores      8753871                       # Number of stores squashed
-system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      4029020                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked      7690355                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               5281102                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               14719425                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles              6525674                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts          619711534                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts          1741377                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts            102747908                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts            87125063                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts          13231258                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                247990                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents              6185988                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents        721236                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect       2486586                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect      2703924                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts             5190510                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts            597504652                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts            106449995                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          6051495                       # Number of squashed instructions skipped in execute
-system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       145675                       # number of nop insts executed
-system.cpu0.iew.exec_refs                   189385273                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches               110604743                       # Number of branches executed
-system.cpu0.iew.exec_stores                  82935278                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.886774                       # Inst execution rate
-system.cpu0.iew.wb_sent                     584170266                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                    582738118                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                287532720                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                500025728                       # num instructions consuming a value
-system.cpu0.iew.wb_rate                      0.864858                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.575036                       # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts       82281412                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls       15225661                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts          4452035                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples    634456144                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.846929                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.842512                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0    437517078     68.96%     68.96% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1     97256113     15.33%     84.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2     33197387      5.23%     89.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3     15688308      2.47%     91.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4     10938676      1.72%     93.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5      6579950      1.04%     94.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6      6141511      0.97%     95.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7      3977023      0.63%     96.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8     23160098      3.65%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total    634456144                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts           457096110                       # Number of instructions committed
-system.cpu0.commit.committedOps             537339276                       # Number of ops (including micro ops) committed
-system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                     164244670                       # Number of memory references committed
-system.cpu0.commit.loads                     85873478                       # Number of loads committed
-system.cpu0.commit.membars                    3759461                       # Number of memory barriers committed
-system.cpu0.commit.branches                 102099172                       # Number of branches committed
-system.cpu0.commit.fp_insts                    454376                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                493297626                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls            13466186                       # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu       371876704     69.21%     69.21% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult        1107747      0.21%     69.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv           49726      0.01%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.42% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc        60429      0.01%     69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead       85873478     15.98%     85.41% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite      78371192     14.59%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total        537339276                       # Class of committed instruction
-system.cpu0.commit.bw_lim_events             23160098                       # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads                  1226917419                       # The number of ROB reads
-system.cpu0.rob.rob_writes                 1253216154                       # The number of ROB writes
-system.cpu0.timesIdled                        4189702                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       25389842                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                 54362488365                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                  457096110                       # Number of Instructions Simulated
-system.cpu0.committedOps                    537339276                       # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi                              1.474080                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        1.474080                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.678389                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.678389                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               703759932                       # number of integer regfile reads
-system.cpu0.int_regfile_writes              416323236                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   842814                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  524896                       # number of floating regfile writes
-system.cpu0.cc_regfile_reads                127590054                       # number of cc regfile reads
-system.cpu0.cc_regfile_writes               128777466                       # number of cc regfile writes
-system.cpu0.misc_regfile_reads             1210356696                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes              15381690                       # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements         10779491                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.983410                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          308062266                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10780003                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            28.577197                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       1667914500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   303.491043                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   208.492367                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.592756                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.407212                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999968                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1359846782                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1359846782                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     81913095                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     81085676                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      162998771                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     68945283                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     67608016                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     136553299                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       203242                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       204927                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       408169                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       172243                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       153828                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       326071                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1807303                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1793639                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3600942                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2085816                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      2057165                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      4142981                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    151030621                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    148847520                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       299878141                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    151233863                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    149052447                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      300286310                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      6333331                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      6515820                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total     12849151                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      6514171                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      6636089                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total     13150260                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       640566                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       698533                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1339099                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       645837                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       595706                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1241543                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       333547                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       322838                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       656385                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data           13                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            8                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data     13493339                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data     13747615                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total      27240954                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data     14133905                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data     14446148                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     28580053                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  98901247500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  99537012000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 198438259500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227853900939                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 237216026267                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 465069927206                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  15046942422                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  13204575493                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  28251517915                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4379004500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   4078607000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   8457611500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data       179500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data       254000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       433500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 341802090861                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 349957613760                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 691759704621                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 341802090861                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 349957613760                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 691759704621                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     88246426                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     87601496                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    175847922                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     75459454                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     74244105                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    149703559                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       843808                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       903460                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1747268                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       818080                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       749534                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1567614                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2140850                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      2116477                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      4257327                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2085829                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      2057173                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      4143002                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    164523960                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    162595135                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    327119095                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    165367768                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    163498595                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    328866363                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.071769                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.074380                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.073070                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.086327                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.089382                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.087842                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.759137                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.773175                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.766396                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.789455                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.794768                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.791995                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.155801                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.152536                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.154178                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000006                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.082014                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.084551                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.083275                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.085470                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.088356                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086905                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15615.992201                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15276.206525                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15443.686474                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34978.188466                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35746.359982                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35365.835140                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23298.359218                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22166.262373                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22755.166688                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13128.598069                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12633.602612                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12885.138295                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13807.692308                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        31750                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20642.857143                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25331.171985                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25455.878257                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 25394.107145                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24183.132040                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24224.977742                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24204.283478                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs     50179402                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        52249                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs          3620965                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets           1011                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    13.858019                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    51.680514                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      8246145                       # number of writebacks
-system.cpu0.dcache.writebacks::total          8246145                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3422225                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data      3613055                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total      7035280                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      5423611                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      5531095                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total     10954706                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         3582                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data         3404                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total         6986                       # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       204425                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data       198944                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total       403369                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      8849418                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      9147554                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total     17996972                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      8849418                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      9147554                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total     17996972                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2911106                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2902765                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5813871                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1090560                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1104994                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2195554                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       631874                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       682564                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1314438                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       642255                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       592302                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1234557                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       129122                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       123894                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       253016                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data           13                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            8                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           21                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4643921                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      4600061                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      9243982                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5275795                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      5282625                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total     10558420                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        17861                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        15819                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33680                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18882                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        14815                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        36743                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        30634                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67377                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  45537932500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  44832999500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  90370932000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  39266250291                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  40577595959                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  79843846250                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10081360000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  12415038000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  22496398000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  14258396422                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  12486057493                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  26744453915                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1802187500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1654747000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3456934500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data       166500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data       246000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       412500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  99062579213                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  97896652952                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 196959232165                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109143939213                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110311690952                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 219455630165                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3399664500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   2864633000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6264297500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3399664500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   2864633000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6264297500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032988                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033136                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033062                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.014452                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014883                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014666                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.748836                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.755500                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.752282                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.785076                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.790227                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.787539                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060313                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.058538                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059431                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000006                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028226                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028292                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028259                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.031903                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.032310                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032106                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15642.828705                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15444.929059                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15544.020843                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36005.584554                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36722.005693                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36366.150070                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15954.699829                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18188.826249                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17114.841476                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22200.522257                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21080.559399                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21663.198957                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13957.245861                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13356.151226                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13662.908670                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12807.692308                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        30750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19642.857143                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21331.667617                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21281.598864                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21306.752021                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20687.676305                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20881.984042                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20784.893020                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190340.098539                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181088.121879                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185994.581354                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92525.501456                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93511.555788                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.826380                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         16451372                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.708511                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          172021238                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         16451884                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.456021                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      12245439500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   287.829103                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   223.879408                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.562166                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.437264                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999431                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        206174057                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       206174057                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst     86244738                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     85776500                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      172021238                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     86244738                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     85776500                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       172021238                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     86244738                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     85776500                       # number of overall hits
-system.cpu0.icache.overall_hits::total      172021238                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      8850303                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      8850359                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     17700662                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      8850303                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      8850359                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      17700662                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      8850303                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      8850359                       # number of overall misses
-system.cpu0.icache.overall_misses::total     17700662                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116359281374                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116489940381                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 232849221755                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 116359281374                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 116489940381                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 232849221755                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 116359281374                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 116489940381                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 232849221755                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     95095041                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     94626859                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    189721900                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     95095041                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     94626859                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    189721900                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     95095041                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     94626859                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    189721900                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.093068                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.093529                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.093298                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.093068                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.093529                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.093298                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.093068                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.093529                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.093298                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13147.491264                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.171205                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13154.831257                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13147.491264                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13162.171205                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13154.831257                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13147.491264                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13162.171205                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13154.831257                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs        90295                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs             7581                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    11.910698                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     16451372                       # number of writebacks
-system.cpu0.icache.writebacks::total         16451372                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       621647                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst       626857                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total      1248504                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst       621647                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst       626857                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total      1248504                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst       621647                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst       626857                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total      1248504                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      8228656                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      8223502                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     16452158                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      8228656                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      8223502                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     16452158                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      8228656                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      8223502                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     16452158                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        12438                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst         8200                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        20638                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        12438                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst         8200                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        20638                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103166162413                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103212304918                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 206378467331                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103166162413                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103212304918                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 206378467331                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103166162413                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103212304918                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 206378467331                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    974276500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst    641521000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   1615797500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    974276500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst    641521000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   1615797500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.086717                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.086717                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.086531                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.086905                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.086717                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12544.157875                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12544.157875                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12537.425603                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12550.894366                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12544.157875                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065                       # average overall mshr uncacheable latency
-system.cpu1.branchPred.lookups              133897441                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted         89938186                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect          5869763                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups            91159166                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits               61608831                       # Number of BTB hits
-system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            67.583803                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS               17197784                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect            191914                       # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups        5022071                       # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits           2642299                       # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses         2379772                       # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted       413417                       # Number of mispredicted indirect branches.
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   900943                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               900943                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        17588                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        92135                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore       552674                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       348269                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean  2521.581019                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15048.371457                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535       345488     99.20%     99.20% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071         1911      0.55%     99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607          471      0.14%     99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143          154      0.04%     99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679          142      0.04%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215           31      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751           66      0.02%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       348269                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       416714                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 22183.198789                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17895.949159                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17072.754814                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535       407840     97.87%     97.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071         7849      1.88%     99.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607          499      0.12%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143          336      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679          108      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215           63      0.02%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751           13      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       416714                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 309953543704                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.014716                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.659727                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 308957195204     99.68%     99.68% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7    543608000      0.18%     99.85% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11    198540500      0.06%     99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15    120617500      0.04%     99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19     43978000      0.01%     99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23     24203000      0.01%     99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27     22128500      0.01%     99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31     36223000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35      6651000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39       321500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43        27000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47        20000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51         8000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::52-55         5500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::56-59         6000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::60-63        11000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 309953543704                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        92135     83.97%     83.97% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        17588     16.03%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       109723                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       900943                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       900943                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       109723                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       109723                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total      1010666                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                   106418453                       # DTB read hits
-system.cpu1.dtb.read_misses                    624156                       # DTB read misses
-system.cpu1.dtb.write_hits                   81533380                       # DTB write hits
-system.cpu1.dtb.write_misses                   276787                       # DTB write misses
-system.cpu1.dtb.flush_tlb                        1086                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              22079                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    541                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   55782                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                      176                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  9564                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    55148                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses               107042609                       # DTB read accesses
-system.cpu1.dtb.write_accesses               81810167                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        187951833                       # DTB hits
-system.cpu1.dtb.misses                         900943                       # DTB misses
-system.cpu1.dtb.accesses                    188852776                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                   102336                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong               102336                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         3041                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        69360                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore        14089                       # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples        88247                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean  1349.994901                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev  8816.342326                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767        87374     99.01%     99.01% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535          501      0.57%     99.58% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303          211      0.24%     99.82% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071          117      0.13%     99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839           19      0.02%     99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607            9      0.01%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::360448-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        88247                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        86490                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27376.708290                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 22843.157676                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18954.672615                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535        84456     97.65%     97.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071         1746      2.02%     99.67% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607          174      0.20%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143           67      0.08%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679           29      0.03%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215            9      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751            4      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        86490                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 610599891424                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean     0.922621                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev     0.267613                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0    47307697252      7.75%      7.75% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1   563239770172     92.24%     99.99% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2       45620000      0.01%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3        5915500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4         874500      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5          14000      0.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 610599891424                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        69360     95.80%     95.80% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         3041      4.20%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        72401                       # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst       102336                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total       102336                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72401                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72401                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       174737                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                    94847182                       # ITB inst hits
-system.cpu1.itb.inst_misses                    102336                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                        1086                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              22079                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    541                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   41108                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                   191650                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                94949518                       # ITB inst accesses
-system.cpu1.itb.hits                         94847182                       # DTB hits
-system.cpu1.itb.misses                         102336                       # DTB misses
-system.cpu1.itb.accesses                     94949518                       # DTB accesses
-system.cpu1.numPwrStateTransitions              16690                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         8345                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    2811784025.136968                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   54125884171.976646                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3484     41.75%     41.75% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         4842     58.02%     99.77% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.82% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.01%     99.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.86% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            3      0.04%     99.89% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows            8      0.10%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 1988782282928                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           8345                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   27852879525232                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 23464337689768                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                       669110072                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles         247318637                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                     594168769                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                  133897441                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches          81448914                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                    382780415                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles               13369418                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                   2469656                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles               22020                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             2942                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles      4831905                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       160199                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles         2485                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                 94635082                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes              3655757                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                  39111                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         644272699                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.077858                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.328781                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               498403789     77.36%     77.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                18180113      2.82%     80.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                18298329      2.84%     83.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                13344455      2.07%     85.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                28485052      4.42%     89.51% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                 9005401      1.40%     90.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 9710824      1.51%     92.42% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                 8365736      1.30%     93.72% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                40479000      6.28%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           644272699                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.200113                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.887999                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles               200592206                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles            318637226                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                105865940                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles             13861849                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               5313208                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved            19620033                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred              1391095                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts             647812132                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts              4304218                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               5313208                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles               208315491                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               23091878                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles     256219950                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                111868936                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles             39460643                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts             632346200                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                89809                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents               2171113                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents               1552755                       # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents              19722377                       # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents            3888                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands          605326116                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            973029596                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       745395954                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           835166                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps            508286647                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                97039469                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts          15581908                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts      13599233                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                 77351395                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads           101957824                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores           85683722                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads         13730276                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores        14508656                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                 599162654                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded           15675959                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                600368831                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           870257                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       82392045                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     51705579                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        355230                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    644272699                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.931855                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.655757                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0          408550840     63.41%     63.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1          100016688     15.52%     78.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2           43398898      6.74%     85.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3           31119922      4.83%     90.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           23055723      3.58%     94.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5           16110351      2.50%     96.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6           11122843      1.73%     98.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7            6496596      1.01%     99.32% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8            4400838      0.68%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      644272699                       # Number of insts issued each cycle
-system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                3033866     25.31%     25.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                 23473      0.20%     25.51% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                   1799      0.02%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     25.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4963680     41.42%     66.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite              3962195     33.06%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass               57      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu            407511218     67.88%     67.88% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult             1473925      0.25%     68.12% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                66979      0.01%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                186      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                  16      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               1      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              9      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp             14      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc         58109      0.01%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead           108674321     18.10%     86.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite           82583972     13.76%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total             600368831                       # Type of FU issued
-system.cpu1.iq.rate                          0.897265                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                   11985013                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019963                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads        1856828451                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes        697391618                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses    577348747                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads            1037180                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            532278                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       459183                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses             611800062                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 553725                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads         4645881                       # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads     16996855                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses        20011                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation       704534                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      8628630                       # Number of stores squashed
-system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads      3900409                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      8595303                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               5313208                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               14601213                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles              6790244                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts          614987274                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts          1737370                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts            101957824                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts            85683722                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts          13306309                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                234327                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents              6472536                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents        704534                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect       2511910                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect      2724374                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts             5236284                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts            593397792                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts            106407717                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          6082445                       # Number of squashed instructions skipped in execute
-system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       148661                       # number of nop insts executed
-system.cpu1.iew.exec_refs                   187941905                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches               109851293                       # Number of branches executed
-system.cpu1.iew.exec_stores                  81534188                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.886846                       # Inst execution rate
-system.cpu1.iew.wb_sent                     579236319                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                    577807930                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                285288573                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                495728954                       # num instructions consuming a value
-system.cpu1.iew.wb_rate                      0.863547                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.575493                       # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts       82442886                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls       15320729                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts          4497993                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    630278595                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.844780                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.835584                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0    433887749     68.84%     68.84% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1     97721864     15.50%     84.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2     32952593      5.23%     89.57% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3     15389192      2.44%     92.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4     10994625      1.74%     93.76% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5      6638239      1.05%     94.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      6092126      0.97%     95.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7      3888165      0.62%     96.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8     22714042      3.60%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    630278595                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts           453286692                       # Number of instructions committed
-system.cpu1.commit.committedOps             532446568                       # Number of ops (including micro ops) committed
-system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                     162016061                       # Number of memory references committed
-system.cpu1.commit.loads                     84960969                       # Number of loads committed
-system.cpu1.commit.membars                    3734725                       # Number of memory barriers committed
-system.cpu1.commit.branches                 101308962                       # Number of branches committed
-system.cpu1.commit.fp_insts                    440790                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                488486887                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls            13305521                       # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu       369191199     69.34%     69.34% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult        1139544      0.21%     69.55% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv           50295      0.01%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.56% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc        49427      0.01%     69.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.57% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead       84960969     15.96%     85.53% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite      77055092     14.47%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total        532446568                       # Class of committed instruction
-system.cpu1.commit.bw_lim_events             22714042                       # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads                  1218446611                       # The number of ROB reads
-system.cpu1.rob.rob_writes                 1243796841                       # The number of ROB writes
-system.cpu1.timesIdled                        4173884                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                       24837373                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                 46928670537                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                  453286692                       # Number of Instructions Simulated
-system.cpu1.committedOps                    532446568                       # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi                              1.476130                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.476130                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.677447                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.677447                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               698541221                       # number of integer regfile reads
-system.cpu1.int_regfile_writes              412892879                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                   836436                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                  478776                       # number of floating regfile writes
-system.cpu1.cc_regfile_reads                127759728                       # number of cc regfile reads
-system.cpu1.cc_regfile_writes               128888879                       # number of cc regfile writes
-system.cpu1.misc_regfile_reads             1201368002                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes              15442226                       # number of misc regfile writes
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40306                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40306                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230970                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230970                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353754                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334312                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334312                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             47813000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               348500                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               14000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25706500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            40142500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568865504                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147730000                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115466                       # number of replacements
-system.iocache.tags.tagsinuse               10.425537                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115482                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13089208816000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     5.904041                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     4.521495                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.369003                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.282593                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.651596                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039722                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039722                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8821                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8858                       # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115485                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115525                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115485                       # number of overall misses
-system.iocache.overall_misses::total           115525                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5166000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1639680634                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1644846634                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12789916870                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12789916870                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5517000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14429597504                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14435114504                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5517000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14429597504                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14435114504                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8821                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8858                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115485                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115525                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115485                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115525                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139621.621622                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185883.758531                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185690.520885                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119908.468368                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119908.468368                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       137925                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124947.807109                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124952.300403                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       137925                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124947.807109                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124952.300403                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         32611                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3377                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.656796                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8821                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8858                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115485                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115525                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115485                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115525                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3316000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1198630634                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1201946634                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7449853156                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7449853156                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3517000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8648483790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8652000790                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3517000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8648483790                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8652000790                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89621.621622                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135883.758531                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135690.520885                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69844.119440                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69844.119440                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        87925                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74888.373295                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74892.887167                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        87925                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74888.373295                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74892.887167                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1423408                       # number of replacements
-system.l2c.tags.tagsinuse                65419.478833                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   53105897                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1486877                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    35.716402                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               2398439000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks    9244.382531                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   234.052326                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   281.998657                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4278.290194                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    23306.302204                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   255.590373                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   270.257283                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2928.362959                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    24620.242304                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.141058                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003571                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.004303                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.065282                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.355626                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003900                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.004124                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.044683                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.375675                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998222                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          371                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        63098                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          370                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          323                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1334                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5382                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55988                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.005661                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.962799                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                449442160                       # Number of tag accesses
-system.l2c.tags.data_accesses               449442160                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       529956                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       175456                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       523339                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       172870                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1401621                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      8246145                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         8246145                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     16447658                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        16447658                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data           13580                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           13715                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               27295                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            13                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                19                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           799517                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           802587                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1602104                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       8182330                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       8175499                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          16357829                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3510444                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3540322                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          7050766                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       354708                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       360482                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           715190                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        529956                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        175456                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             8182330                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4309961                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        523339                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        172870                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             8175499                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4342909                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                26412320                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       529956                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       175456                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            8182330                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4309961                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       523339                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       172870                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            8175499                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4342909                       # number of overall hits
-system.l2c.overall_hits::total               26412320                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         2865                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2437                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2846                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2323                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                10471                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1976                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          2155                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4131                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         282504                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         292518                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             575022                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        46080                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        47726                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           93806                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       154642                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       162923                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         317565                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       287547                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       231820                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         519367                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         2865                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2437                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             46080                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            437146                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2846                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2323                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             47726                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            455441                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                996864                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         2865                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2437                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            46080                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           437146                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2846                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2323                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            47726                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           455441                       # number of overall misses
-system.l2c.overall_misses::total               996864                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    253277500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    220942000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    251257000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    208508500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      933985000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     35028000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     39186500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     74214500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       168000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       168000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  28813882500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  29989617500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  58803500000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3981410000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst   4106130500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   8087540500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  14012396500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  15181111500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  29193508000                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data       688000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data       144500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total       832500                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    253277500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    220942000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3981410000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  42826279000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    251257000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    208508500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   4106130500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  45170729000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     97018533500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    253277500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    220942000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3981410000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  42826279000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    251257000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    208508500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   4106130500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  45170729000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    97018533500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       532821                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       177893                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       526185                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       175193                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1412092                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      8246145                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      8246145                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     16447658                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     16447658                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        15556                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        15870                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           31426                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           13                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            8                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            21                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1082021                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1095105                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2177126                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      8228410                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      8223225                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      16451635                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      3665086                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data      3703245                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      7368331                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       642255                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       592302                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1234557                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       532821                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       177893                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         8228410                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         4747107                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       526185                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       175193                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         8223225                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         4798350                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            27409184                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       532821                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       177893                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        8228410                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4747107                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       526185                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       175193                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        8223225                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        4798350                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           27409184                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.007415                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.127025                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.135791                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.131452                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.095238                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.261089                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.267114                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.264120                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005600                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005804                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005702                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.042193                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.043995                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.043099                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.447715                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.391388                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.420691                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005600                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.092087                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005804                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.094916                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.036370                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.005377                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.013699                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005600                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.092087                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.005409                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.013260                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005804                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.094916                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.036370                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88404.013962                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 90661.469019                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88284.258609                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89758.286698                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 89197.306847                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17726.720648                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18183.990719                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 17965.262648                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        84000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        84000                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101994.600076                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102522.297773                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 102263.043849                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 86402.126736                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 86035.504756                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 86215.599215                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90611.842190                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93179.670765                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 91929.236534                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     2.392652                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     0.623328                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     1.602913                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88404.013962                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90661.469019                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 86402.126736                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 97967.907747                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88284.258609                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89758.286698                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 86035.504756                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 99180.198972                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 97323.740751                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88404.013962                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90661.469019                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 86402.126736                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 97967.907747                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88284.258609                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89758.286698                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 86035.504756                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 99180.198972                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 97323.740751                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1205359                       # number of writebacks
-system.l2c.writebacks::total                  1205359                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.itb.walker           24                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.itb.walker           25                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                49                       # number of ReadReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu0.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu0.data           13                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu1.data            9                       # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total           22                       # number of ReadSharedReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.itb.walker           24                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             13                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.itb.walker           25                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data              9                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 72                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.itb.walker           24                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            13                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.itb.walker           25                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data             9                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                72                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         2865                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2413                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2846                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2298                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           10422                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1976                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         2155                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         4131                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       282504                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       292518                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        575022                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        46079                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        47726                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        93805                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       154629                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       162914                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       317543                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       287547                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       231820                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       519367                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         2865                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2413                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        46079                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       437133                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2846                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2298                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        47726                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       455432                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           996792                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         2865                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         2413                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        46079                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       437133                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2846                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2298                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        47726                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       455432                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          996792                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        12438                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        17861                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst         8200                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        15819                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        54318                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18882                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        14815                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        33697                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        12438                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        36743                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst         8200                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        30634                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total        88015                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    224626003                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    195186501                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    222795004                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    183490000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    826097508                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     37692500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     41197500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     78890000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data       148000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       148000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  25988823538                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  27064433009                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  53053256547                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   3520582539                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   3628854532                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   7149437071                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  12465114109                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  13551116075                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  26016230184                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   5983135505                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   4845340006                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total  10828475511                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    224626003                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    195186501                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   3520582539                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  38453937647                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    222795004                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    183490000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   3628854532                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  40615549084                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  87045021310                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    224626003                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    195186501                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   3520582539                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  38453937647                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    222795004                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    183490000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   3628854532                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  40615549084                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  87045021310                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    781472499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   3176322000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst    514421000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2666808000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   7139023499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    781472499                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3176322000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst    514421000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2666808000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   7139023499                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005377                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013564                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.005409                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013117                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.007381                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.127025                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.135791                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.131452                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.095238                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.261089                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.267114                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.264120                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005702                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.042190                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.043992                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.043096                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.447715                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.391388                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.420691                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.005377                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013564                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.092084                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.005409                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013117                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.094914                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.036367                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.005377                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013564                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005600                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.092084                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.005409                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013117                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005804                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.094914                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.036367                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 79264.777202                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19075.151822                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19117.169374                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19097.070927                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        74000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        74000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91994.532955                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92522.282420                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 92263.003062                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76215.948734                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80613.042243                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83179.567594                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81929.786467                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20807.504530                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20901.302761                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20849.371468                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87968.507633                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89180.270785                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 87325.160425                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76403.188850                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87968.507633                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76035.170180                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89180.270785                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 87325.160425                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177835.619506                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168582.590556                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131430.161254                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86446.996707                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87053.861722                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.441220                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       3173701                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1572230                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3254                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               54318                       # Transaction distribution
-system.membus.trans_dist::ReadResp             484946                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33697                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33697                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1311989                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           225778                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4711                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            574465                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           574465                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        430628                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        626011                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           78                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6864                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3984552                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4114198                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       237454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4351652                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port         2212                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13728                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    142199148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    142370922                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7237952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7237952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               149608874                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3063                       # Total snoops (count)
-system.membus.snoopTraffic                     195520                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1723835                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019089                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.136837                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1690929     98.09%     98.09% # Request fanout histogram
-system.membus.snoop_fanout::1                   32906      1.91%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1723835                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           114103500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               51156                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5424500                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8729629317                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         5464439160                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44651356                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
-system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
-system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
-system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
-system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
-system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     55313500                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     28081340                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         5055                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           1866                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         1866                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317217215000                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            2056199                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          25877432                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33697                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9451504                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     16451372                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2751395                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           31429                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            21                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          31450                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2177126                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2177126                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      16452157                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      7370941                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1264166                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1234557                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     49396440                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     32537915                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       866839                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      2547134                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              85348328                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   2107113280                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1138900522                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2824688                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      8472048                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             3257310538                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         2046689                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  81942376                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         30811624                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.026814                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.161540                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               29985433     97.32%     97.32% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 826191      2.68%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           30811624                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        53009049492                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1413410                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       24725297607                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       15008598618                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         514146176                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1491177210                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16436                       # number of quiesce instructions executed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/system.terminal
deleted file mode 100644 (file)
index 84cd483..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-[    0.000000] Initializing cgroup subsys cpu\r
-[    0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[    0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[    0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[    0.000000] Memory limited to 256MB\r
-[    0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[    0.000000] On node 0 totalpages: 65536\r
-[    0.000000]   DMA zone: 896 pages used for memmap\r
-[    0.000000]   DMA zone: 0 pages reserved\r
-[    0.000000]   DMA zone: 65536 pages, LIFO batch:15\r
-[    0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[    0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 64640\r
-[    0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[    0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[    0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[    0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[    0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[    0.000000] Virtual kernel memory layout:\r
-[    0.000000]     vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000   (245759 MB)\r
-[    0.000000]     vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000   (     3 MB)\r
-[    0.000000]     modules : 0xffffffbffc000000 - 0xffffffc000000000   (    64 MB)\r
-[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc010000000   (   256 MB)\r
-[    0.000000]       .init : 0xffffffc000692000 - 0xffffffc0006c6200   (   209 kB)\r
-[    0.000000]       .text : 0xffffffc000080000 - 0xffffffc0006914e4   (  6214 kB)\r
-[    0.000000]       .data : 0xffffffc0006c7000 - 0xffffffc0007141e0   (   309 kB)\r
-[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[    0.000000] Preemptible hierarchical RCU implementation.\r
-[    0.000000]         RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[    0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[    0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[    0.000011] Console: colour dummy device 80x25\r
-[    0.000013] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[    0.000013] pid_max: default: 32768 minimum: 301\r
-[    0.000020] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000021] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000088] hw perfevents: no hardware support available\r
-[    1.060050] CPU1: failed to come online\r
-[    2.080097] CPU2: failed to come online\r
-[    3.100143] CPU3: failed to come online\r
-[    3.100145] Brought up 1 CPUs\r
-[    3.100146] SMP: Total of 1 processors activated.\r
-[    3.100181] devtmpfs: initialized\r
-[    3.100440] atomic64_test: passed\r
-[    3.100467] regulator-dummy: no parameters\r
-[    3.100681] NET: Registered protocol family 16\r
-[    3.100757] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[    3.100763] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[    3.100915] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[    3.100918] Serial: AMBA PL011 UART driver\r
-[    3.101033] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[    3.101053] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[    3.101608] console [ttyAMA0] enabled\r
-[    3.101661] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[    3.101686] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[    3.101712] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[    3.101737] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[    3.130357] 3V3: 3300 mV \r
-[    3.130385] vgaarb: loaded\r
-[    3.130416] SCSI subsystem initialized\r
-[    3.130445] libata version 3.00 loaded.\r
-[    3.130474] usbcore: registered new interface driver usbfs\r
-[    3.130488] usbcore: registered new interface driver hub\r
-[    3.130512] usbcore: registered new device driver usb\r
-[    3.130531] pps_core: LinuxPPS API ver. 1 registered\r
-[    3.130540] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[    3.130556] PTP clock support registered\r
-[    3.130629] Switched to clocksource arch_sys_counter\r
-[    3.131305] NET: Registered protocol family 2\r
-[    3.131350] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[    3.131365] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[    3.131381] TCP: Hash tables configured (established 2048 bind 2048)\r
-[    3.131394] TCP: reno registered\r
-[    3.131400] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131412] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.131439] NET: Registered protocol family 1\r
-[    3.131480] RPC: Registered named UNIX socket transport module.\r
-[    3.131490] RPC: Registered udp transport module.\r
-[    3.131498] RPC: Registered tcp transport module.\r
-[    3.131506] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[    3.131518] PCI: CLS 0 bytes, default 64\r
-[    3.131611] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[    3.131673] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[    3.132676] fuse init (API version 7.23)\r
-[    3.132730] msgmni has been set to 469\r
-[    3.134207] io scheduler noop registered\r
-[    3.134242] io scheduler cfq registered (default)\r
-[    3.134452] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[    3.134464] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
-[    3.134475] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[    3.134487] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[    3.134496] pci_bus 0000:00: scanning bus\r
-[    3.134505] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[    3.134517] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[    3.134530] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.134557] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[    3.134568] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
-[    3.134578] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
-[    3.134588] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
-[    3.134598] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
-[    3.134608] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
-[    3.134618] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.134644] pci_bus 0000:00: fixups for bus\r
-[    3.134652] pci_bus 0000:00: bus scan returning with max=00\r
-[    3.134662] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[    3.134678] pci 0000:00:00.0: fixup irq: got 33\r
-[    3.134686] pci 0000:00:00.0: assigning IRQ 33\r
-[    3.134695] pci 0000:00:01.0: fixup irq: got 34\r
-[    3.134703] pci 0000:00:01.0: assigning IRQ 34\r
-[    3.134713] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[    3.134725] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[    3.134737] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[    3.134750] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
-[    3.134760] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
-[    3.134771] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
-[    3.134782] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
-[    3.134792] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
-[    3.135096] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[    3.135251] ata_piix 0000:00:01.0: version 2.13\r
-[    3.135261] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[    3.135277] ata_piix 0000:00:01.0: enabling bus mastering\r
-[    3.135444] scsi0 : ata_piix\r
-[    3.135507] scsi1 : ata_piix\r
-[    3.135527] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[    3.135539] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[    3.135605] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[    3.135616] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[    3.135630] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[    3.135640] e1000 0000:00:00.0: enabling bus mastering\r
-[    3.290649] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[    3.290659] ata1.00: 2096640 sectors, multi 0: LBA \r
-[    3.290682] ata1.00: configured for UDMA/33\r
-[    3.290715] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
-[    3.290789] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[    3.290808] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[    3.290839] sd 0:0:0:0: [sda] Write Protect is off\r
-[    3.290847] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[    3.290864] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[    3.290949]  sda: sda1\r
-[    3.291024] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[    3.410900] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[    3.410913] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[    3.410930] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[    3.410939] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[    3.410955] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[    3.410967] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[    3.411012] usbcore: registered new interface driver usb-storage\r
-[    3.411049] mousedev: PS/2 mouse device common for all mice\r
-[    3.411145] usbcore: registered new interface driver usbhid\r
-[    3.411154] usbhid: USB HID core driver\r
-[    3.411176] TCP: cubic registered\r
-[    3.411183] NET: Registered protocol family 17\r
-\0[    3.411407] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[    3.411435] devtmpfs: mounted\r
-[    3.411454] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[    3.447841] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[    3.542532] random: dd urandom read with 19 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[    3.660857] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
deleted file mode 100644 (file)
index f55dd08..0000000
+++ /dev/null
@@ -1,1799 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxArmSystem
-children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
-atags_addr=134217728
-boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
-boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-cache_line_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
-early_kernel_symbols=false
-enable_context_switch_stats_dump=false
-eventq_index=0
-exit_on_work_items=false
-flags_addr=469827632
-gic_cpu_addr=738205696
-have_large_asid_64=false
-have_lpae=true
-have_security=false
-have_virtualization=false
-highest_el_is_64=false
-init_param=0
-kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
-kernel_addr_check=true
-load_addr_mask=268435455
-load_offset=2147483648
-machine_type=VExpress_EMM64
-mem_mode=timing
-mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.nvmem system.realview.vram
-mmap_using_noreserve=false
-multi_proc=true
-multi_thread=false
-num_work_ids=16
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-panic_on_oops=true
-panic_on_panic=true
-phys_addr_range_64=40
-power_model=Null
-readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
-reset_addr_64=0
-symbolfile=
-thermal_components=
-thermal_model=Null
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-delay=50000
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.cf0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.cf0.image
-
-[system.cf0.image]
-type=CowDiskImage
-children=child
-child=system.cf0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.cf0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
-read_only=true
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu0.dstage2_mmu
-dtb=system.cpu0.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-istage2_mmu=system.cpu0.istage2_mmu
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.dtb
-
-[system.cpu0.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu0.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=ArmInterrupts
-eventq_index=0
-
-[system.cpu0.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu0.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu0.itb
-
-[system.cpu0.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu0.istage2_mmu.stage2_tlb.walker
-
-[system.cpu0.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu0.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dstage2_mmu dtb isa istage2_mmu itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-default_p_state=UNDEFINED
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dstage2_mmu=system.cpu1.dstage2_mmu
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu1.isa
-istage2_mmu=system.cpu1.istage2_mmu
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-workload=
-
-[system.cpu1.dstage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.dtb
-
-[system.cpu1.dstage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
-
-[system.cpu1.dstage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.dtb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.isa]
-type=ArmISA
-decoderFlavour=Generic
-eventq_index=0
-fpsid=1090793632
-id_aa64afr0_el1=0
-id_aa64afr1_el1=0
-id_aa64dfr0_el1=1052678
-id_aa64dfr1_el1=0
-id_aa64isar0_el1=0
-id_aa64isar1_el1=0
-id_aa64mmfr0_el1=15728642
-id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
-id_isar0=34607377
-id_isar1=34677009
-id_isar2=555950401
-id_isar3=17899825
-id_isar4=268501314
-id_isar5=0
-id_mmfr0=270536963
-id_mmfr1=0
-id_mmfr2=19070976
-id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
-midr=1091551472
-pmu=Null
-system=system
-
-[system.cpu1.istage2_mmu]
-type=ArmStage2MMU
-children=stage2_tlb
-eventq_index=0
-stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
-sys=system
-tlb=system.cpu1.itb
-
-[system.cpu1.istage2_mmu.stage2_tlb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=true
-size=32
-walker=system.cpu1.istage2_mmu.stage2_tlb.walker
-
-[system.cpu1.istage2_mmu.stage2_tlb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=true
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.itb]
-type=ArmTLB
-children=walker
-eventq_index=0
-is_stage2=false
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=ArmTableWalker
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-is_stage2=false
-num_squash_per_cycle=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sys=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-response_latency=2
-use_default_range=false
-width=16
-master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side
-slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=2147483648:2415919103
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[3]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=50
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-default_p_state=UNDEFINED
-demand_mshr_reserve=1
-eventq_index=0
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-hit_latency=20
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder snoop_filter
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=true
-power_model=Null
-response_latency=2
-snoop_filter=system.membus.snoop_filter
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port
-slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=0
-pio_latency=100000
-pio_size=8
-power_model=Null
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=warn
-pio=system.membus.default
-
-[system.membus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=1
-max_capacity=8388608
-system=system
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-page_policy=open_adaptive
-power_model=Null
-range=2147483648:2415919103
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[5]
-
-[system.realview]
-type=RealView
-children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.realview.aaci_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470024192
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[18]
-
-[system.realview.cf_ctrl]
-type=IdeController
-BAR0=471465984
-BAR0LegacyIO=true
-BAR0Size=256
-BAR1=471466240
-BAR1LegacyIO=true
-BAR1Size=4096
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=1
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=31
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=2
-default_p_state=UNDEFINED
-disks=
-eventq_index=0
-host=system.realview.pci_host
-io_shift=2
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=2
-pci_dev=0
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.realview.clcd]
-type=Pl111
-amba_id=1315089
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=46
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471793664
-pio_latency=10000
-pixel_clock=41667
-power_model=Null
-system=system
-vnc=system.vncserver
-dma=system.iobus.slave[1]
-pio=system.iobus.master[5]
-
-[system.realview.dcc]
-type=SubSystem
-children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.dcc.osc_cpu]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_ddr]
-type=RealViewOsc
-dcc=0
-device=8
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_hsbm]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=25000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_pxl]
-type=RealViewOsc
-dcc=0
-device=5
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_smb]
-type=RealViewOsc
-dcc=0
-device=6
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.dcc.osc_sys]
-type=RealViewOsc
-dcc=0
-device=7
-eventq_index=0
-freq=16667
-parent=system.realview.realview_io
-position=0
-site=1
-voltage_domain=system.voltage_domain
-
-[system.realview.energy_ctrl]
-type=EnergyCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-dvfs_handler=system.dvfs_handler
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470286336
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[22]
-
-[system.realview.ethernet]
-type=IGbE
-BAR0=0
-BAR0LegacyIO=false
-BAR0Size=131072
-BAR1=0
-BAR1LegacyIO=false
-BAR1Size=0
-BAR2=0
-BAR2LegacyIO=false
-BAR2Size=0
-BAR3=0
-BAR3LegacyIO=false
-BAR3Size=0
-BAR4=0
-BAR4LegacyIO=false
-BAR4Size=0
-BAR5=0
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=2
-Command=0
-DeviceID=4213
-ExpansionROM=0
-HeaderType=0
-InterruptLine=1
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=255
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=0
-Revision=0
-Status=0
-SubClassCode=0
-SubsystemID=4104
-SubsystemVendorID=32902
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-default_p_state=UNDEFINED
-eventq_index=0
-fetch_comp_delay=10000
-fetch_delay=10000
-hardware_address=00:90:00:00:00:01
-host=system.realview.pci_host
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=0
-pci_func=0
-phy_epid=896
-phy_pid=680
-pio_latency=30000
-power_model=Null
-rx_desc_cache_size=64
-rx_fifo_size=393216
-rx_write_delay=0
-system=system
-tx_desc_cache_size=64
-tx_fifo_size=393216
-tx_read_delay=0
-wb_comp_delay=10000
-wb_delay=10000
-dma=system.iobus.slave[4]
-pio=system.iobus.master[24]
-
-[system.realview.generic_timer]
-type=GenericTimer
-eventq_index=0
-gic=system.realview.gic
-int_phys=29
-int_virt=27
-system=system
-
-[system.realview.gic]
-type=Pl390
-clk_domain=system.clk_domain
-cpu_addr=738205696
-cpu_pio_delay=10000
-default_p_state=UNDEFINED
-dist_addr=738201600
-dist_pio_delay=10000
-eventq_index=0
-gem5_extensions=true
-int_latency=10000
-it_lines=128
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-platform=system.realview
-power_model=Null
-system=system
-pio=system.membus.master[2]
-
-[system.realview.hdlcd]
-type=HDLcd
-amba_id=1314816
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-enable_capture=true
-eventq_index=0
-gic=system.realview.gic
-int_num=117
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=721420288
-pio_latency=10000
-pixel_buffer_size=2048
-pixel_chunk=32
-power_model=Null
-pxl_clk=system.realview.dcc.osc_pxl
-system=system
-vnc=system.vncserver
-workaround_dma_line_count=true
-workaround_swap_rb=true
-dma=system.membus.slave[0]
-pio=system.iobus.master[6]
-
-[system.realview.ide]
-type=IdeController
-BAR0=1
-BAR0LegacyIO=false
-BAR0Size=8
-BAR1=1
-BAR1LegacyIO=false
-BAR1Size=4
-BAR2=1
-BAR2LegacyIO=false
-BAR2Size=8
-BAR3=1
-BAR3LegacyIO=false
-BAR3Size=4
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=2
-InterruptPin=2
-LatencyTimer=0
-LegacyIOBase=0
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=133
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-default_p_state=UNDEFINED
-disks=system.cf0
-eventq_index=0
-host=system.realview.pci_host
-io_shift=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_bus=0
-pci_dev=1
-pci_func=0
-pio_latency=30000
-power_model=Null
-system=system
-dma=system.iobus.slave[3]
-pio=system.iobus.master[23]
-
-[system.realview.kmi0]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=44
-is_mouse=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470155264
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[7]
-
-[system.realview.kmi1]
-type=Pl050
-amba_id=1314896
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=1000000
-int_num=45
-is_mouse=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470220800
-pio_latency=100000
-power_model=Null
-system=system
-vnc=system.vncserver
-pio=system.iobus.master[8]
-
-[system.realview.l2x0_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=739246080
-pio_latency=100000
-pio_size=4095
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.realview.lan_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=436207616
-pio_latency=100000
-pio_size=65535
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[19]
-
-[system.realview.local_cpu_timer]
-type=CpuLocalTimer
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num_timer=29
-int_num_watchdog=30
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=738721792
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.membus.master[4]
-
-[system.realview.mcc]
-type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
-eventq_index=0
-thermal_domain=Null
-
-[system.realview.mcc.osc_clcd]
-type=RealViewOsc
-dcc=0
-device=1
-eventq_index=0
-freq=42105
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_mcc]
-type=RealViewOsc
-dcc=0
-device=0
-eventq_index=0
-freq=20000
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_peripheral]
-type=RealViewOsc
-dcc=0
-device=2
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.osc_system_bus]
-type=RealViewOsc
-dcc=0
-device=4
-eventq_index=0
-freq=41667
-parent=system.realview.realview_io
-position=0
-site=0
-voltage_domain=system.voltage_domain
-
-[system.realview.mcc.temp_crtl]
-type=RealViewTemperatureSensor
-dcc=0
-device=0
-eventq_index=0
-parent=system.realview.realview_io
-position=0
-site=0
-system=system
-
-[system.realview.mmc_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470089728
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[21]
-
-[system.realview.nvmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=0:67108863
-port=system.membus.master[1]
-
-[system.realview.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=805306368
-conf_device_bits=12
-conf_size=268435456
-default_p_state=UNDEFINED
-eventq_index=0
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=788529152
-platform=system.realview
-power_model=Null
-system=system
-pio=system.iobus.master[2]
-
-[system.realview.realview_io]
-type=RealViewCtrl
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-idreg=35979264
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469827584
-pio_latency=100000
-power_model=Null
-proc_id0=335544320
-proc_id1=335544320
-system=system
-pio=system.iobus.master[1]
-
-[system.realview.rtc]
-type=PL031
-amba_id=3412017
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=36
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=471269376
-pio_latency=100000
-power_model=Null
-system=system
-time=Thu Jan  1 00:00:00 2009
-pio=system.iobus.master[10]
-
-[system.realview.sp810_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=true
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=469893120
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[16]
-
-[system.realview.timer0]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=34
-int_num1=34
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470876160
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[3]
-
-[system.realview.timer1]
-type=Sp804
-amba_id=1316868
-clk_domain=system.clk_domain
-clock0=1000000
-clock1=1000000
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-int_num0=35
-int_num1=35
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470941696
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[4]
-
-[system.realview.uart]
-type=Pl011
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-end_on_eot=false
-eventq_index=0
-gic=system.realview.gic
-int_delay=100000
-int_num=37
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470351872
-pio_latency=100000
-platform=system.realview
-power_model=Null
-system=system
-terminal=system.terminal
-pio=system.iobus.master[0]
-
-[system.realview.uart1_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470417408
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[13]
-
-[system.realview.uart2_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470482944
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[14]
-
-[system.realview.uart3_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470548480
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[15]
-
-[system.realview.usb_fake]
-type=IsaFake
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-fake_mem=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=452984832
-pio_latency=100000
-pio_size=131071
-power_model=Null
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[20]
-
-[system.realview.vgic]
-type=VGic
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-gic=system.realview.gic
-hv_addr=738213888
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_delay=10000
-platform=system.realview
-power_model=Null
-ppint=25
-system=system
-vcpu_addr=738222080
-pio=system.membus.master[3]
-
-[system.realview.vram]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=false
-default_p_state=UNDEFINED
-eventq_index=0
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-power_model=Null
-range=402653184:436207615
-port=system.iobus.master[11]
-
-[system.realview.watchdog_fake]
-type=AmbaFake
-amba_id=0
-clk_domain=system.clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-ignore_access=false
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-pio_addr=470745088
-pio_latency=100000
-power_model=Null
-system=system
-pio=system.iobus.master[17]
-
-[system.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-default_p_state=UNDEFINED
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-p_state_clk_gate_bins=20
-p_state_clk_gate_max=1000000000000
-p_state_clk_gate_min=1000
-point_of_coherency=false
-power_model=Null
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.vncserver]
-type=VncServer
-eventq_index=0
-frame_capture=false
-number=0
-port=5900
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
deleted file mode 100755 (executable)
index 2fb53d9..0000000
+++ /dev/null
@@ -1,1666 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
-warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: ClockedObject: More than one power state change request encountered within the same simulation tick
-warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
-warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
-warn: ClockedObject: Already in the requested power state, request ignored
-warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
deleted file mode 100755 (executable)
index 43fe4b5..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simerr
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:39:41
-gem5 executing on e108600-lin, pid 23105
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
-
-Selected 64-bit ARM architecture, updating default disk image...
-Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
deleted file mode 100644 (file)
index bda055a..0000000
+++ /dev/null
@@ -1,2259 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                 51.820973                       # Number of seconds simulated
-sim_ticks                                51820973246500                       # Number of ticks simulated
-final_tick                               51820973246500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 758799                       # Simulator instruction rate (inst/s)
-host_op_rate                                   891661                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            43998522404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 681336                       # Number of bytes of host memory used
-host_seconds                                  1177.79                       # Real time elapsed on the host
-sim_insts                                   893704771                       # Number of instructions simulated
-sim_ops                                    1050188306                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker       125632                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker       134272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst          2648688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         26060912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker       150272                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker       137792                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst          2660612                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         25358744                       # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide        379264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             57656188                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst      2648688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst      2660612                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         5309300                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     78776832                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data             4                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data         20576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          78797412                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker         1963                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         2098                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             65667                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            407205                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker         2348                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         2153                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst             57698                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data            396240                       # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide           5926                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                941298                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1230888                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data                1                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data             2572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1233461                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker          2424                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker          2591                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               51112                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data              502903                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker          2900                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          2659                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               51342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              489353                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide             7319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1112603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          51112                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          51342                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             102455                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1520173                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data                  0                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                397                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1520570                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1520173                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker         2424                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker         2591                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              51112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data             502903                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker         2900                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         2659                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              51342                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             489750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide            7319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2633173                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        941298                       # Number of read requests accepted
-system.physmem.writeReqs                      1233461                       # Number of write requests accepted
-system.physmem.readBursts                      941298                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1233461                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 60206144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     36928                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  78797632                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  57656188                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               78797412                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      577                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               57499                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               62142                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               57490                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               55825                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               53833                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               61722                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               53577                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               53386                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               55741                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              100411                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              55379                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              62273                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              51298                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              56710                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              52113                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              51322                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               75972                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               80204                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               78083                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               78701                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               75891                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               81886                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               74948                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               74400                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               74844                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               78454                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              75419                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              80852                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              73391                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              78907                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              74453                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              74808                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          19                       # Number of times write queue was full causing retry
-system.physmem.totGap                    51820970325500                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
-system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  898182                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
-system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1230888                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    907166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     28188                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       382                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       299                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       464                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       455                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       288                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      345                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      154                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      121                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      102                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                       98                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       89                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                       65                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                       45                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1619                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1583                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      1562                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      1543                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      1521                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      1511                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      1493                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1484                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1430                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1405                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    33965                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    39434                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    66705                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    69572                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    73099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    70516                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    69275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    71602                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    74263                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    71156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    76473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    74873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    70803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    68999                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    68901                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    66607                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    66114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    65182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     1385                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                     1071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      886                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      685                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                      547                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                      569                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                      375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                      341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      329                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                      294                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                      256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                      327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                      215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                      240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                      223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                      230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                      155                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                      160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                      173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                      162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                      147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                      151                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                      157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       97                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       83                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                       61                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       566411                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      245.410940                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     147.848960                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     286.502889                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         251457     44.39%     44.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       147984     26.13%     70.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        50578      8.93%     79.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        27084      4.78%     84.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        18527      3.27%     87.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12015      2.12%     89.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         8676      1.53%     91.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         7490      1.32%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        42600      7.52%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         566411                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         65859                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        14.283773                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      106.722670                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          65854     99.99%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           65859                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         65859                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        18.694681                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.068066                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        6.774692                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3               123      0.19%      0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                75      0.11%      0.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11               55      0.08%      0.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15             134      0.20%      0.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           51847     78.72%     79.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23            9800     14.88%     94.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27            1125      1.71%     95.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31             552      0.84%     96.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             892      1.35%     98.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39             360      0.55%     98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              86      0.13%     98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47              48      0.07%     98.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              56      0.09%     98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55              44      0.07%     98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59              24      0.04%     99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63              39      0.06%     99.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             432      0.66%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71              30      0.05%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75              32      0.05%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79              26      0.04%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83              20      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.00%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               4      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99               6      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             2      0.00%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             7      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123             2      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             3      0.00%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131            17      0.03%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             2      0.00%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175             1      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179             2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           65859                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    12279482516                       # Total ticks spent queuing
-system.physmem.totMemAccLat               29918001266                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4703605000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13053.27                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31803.27                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.11                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        1.52                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     706352                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    899170                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.09                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.03                       # Row buffer hit rate for writes
-system.physmem.avgGap                     23828373.78                       # Average gap between requests
-system.physmem.pageHitRate                      73.92                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 2184439320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 1191906375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                3552658200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               4018150800                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           1306740976245                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           29946315984000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             34648697732700                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.623145                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   49817760765674                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    1730415960000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    272796109326                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 2097627840                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 1144539000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                3784926600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3960109440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           3384693617760                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           1304293519080                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           29948462876250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             34648437215970                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.618118                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   49821299610951                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    1730415960000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    269251106549                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks                   131570                       # Table walker walks requested
-system.cpu0.dtb.walker.walksLong               131570                       # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        20583                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3        94968                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore            7                       # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples       131563                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0         131563    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total       131563                       # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples       115558                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 24585.701552                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 21339.790503                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 14301.317993                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535       114596     99.17%     99.17% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071          825      0.71%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607           55      0.05%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143           40      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679           25      0.02%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total       115558                       # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples   4911919556                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean     1.054990                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0     -270104796     -5.50%     -5.50% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1     5182024352    105.50%    100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total   4911919556                       # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K        94969     82.19%     82.19% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M        20583     17.81%    100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total       115552                       # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       131570                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       131570                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       115552                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       115552                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total       247122                       # Table walker requests started/completed, data/inst
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    83870325                       # DTB read hits
-system.cpu0.dtb.read_misses                    100143                       # DTB read misses
-system.cpu0.dtb.write_hits                   76256860                       # DTB write hits
-system.cpu0.dtb.write_misses                    31427                       # DTB write misses
-system.cpu0.dtb.flush_tlb                       51828                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                   73309                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                  4917                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                     9888                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                83970468                       # DTB read accesses
-system.cpu0.dtb.write_accesses               76288287                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                        160127185                       # DTB hits
-system.cpu0.dtb.misses                         131570                       # DTB misses
-system.cpu0.dtb.accesses                    160258755                       # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks                    77633                       # Table walker walks requested
-system.cpu0.itb.walker.walksLong                77633                       # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2         4406                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3        67615                       # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples        77633                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0          77633    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total        77633                       # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples        72021                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 27701.552325                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24376.545883                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 16846.806682                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535        70875     98.41%     98.41% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071          990      1.37%     99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607           61      0.08%     99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143           51      0.07%     99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679           30      0.04%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215            8      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total        72021                       # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples   -294749296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0     -294749296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total   -294749296                       # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K        67615     93.88%     93.88% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M         4406      6.12%    100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total        72021                       # Table walker page sizes translated
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        77633                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total        77633                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        72021                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total        72021                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total       149654                       # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits                   447669719                       # ITB inst hits
-system.cpu0.itb.inst_misses                     77633                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                       51828                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid              21293                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                    538                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                   53432                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses               447747352                       # ITB inst accesses
-system.cpu0.itb.hits                        447669719                       # DTB hits
-system.cpu0.itb.misses                          77633                       # DTB misses
-system.cpu0.itb.accesses                    447747352                       # DTB accesses
-system.cpu0.numPwrStateTransitions              16472                       # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples         8236                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean    5647358953.626396                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev   114048668982.955048                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows         3496     42.45%     42.45% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10         4676     56.78%     99.22% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::5e+10-1e+11            1      0.01%     99.24% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            4      0.05%     99.28% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11           45      0.55%     99.83% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.85% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::overflows           10      0.12%    100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 5700356989224                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total           8236                       # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON   5309324904433                       # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 46511648342067                       # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles                     51821514544                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   16340                       # number of quiesce instructions executed
-system.cpu0.committedInsts                  447398457                       # Number of instructions committed
-system.cpu0.committedOps                    525429864                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            482287917                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                434588                       # Number of float alu accesses
-system.cpu0.num_func_calls                   26374142                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     68421724                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   482287917                       # number of integer instructions
-system.cpu0.num_fp_insts                       434588                       # number of float instructions
-system.cpu0.num_int_register_reads          704372154                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         382730581                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              702801                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             363748                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads           117948117                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes          117634638                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                    160118732                       # number of memory refs
-system.cpu0.num_load_insts                   83867967                       # Number of load instructions
-system.cpu0.num_store_insts                  76250765                       # Number of store instructions
-system.cpu0.num_idle_cycles              50235171233.913414                       # Number of idle cycles
-system.cpu0.num_busy_cycles              1586343310.086583                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.030612                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.969388                       # Percentage of idle cycles
-system.cpu0.Branches                         99895335                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu                364386062     69.31%     69.31% # Class of executed instruction
-system.cpu0.op_class::IntMult                 1119710      0.21%     69.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    49931      0.01%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc             52613      0.01%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
-system.cpu0.op_class::MemRead                83867967     15.95%     85.50% # Class of executed instruction
-system.cpu0.op_class::MemWrite               76250765     14.50%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 525727049                       # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements         10225430                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.965656                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs          309996830                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs         10225942                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            30.314746                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle       3504381500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.556484                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   262.409172                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.487415                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.512518                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999933                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          404                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses       1291585318                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses      1291585318                       # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data     78353332                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data     78391099                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total      156744431                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data     72326748                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data     72506340                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total     144833088                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data       195506                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data       198980                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total       394486                       # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data       165435                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data       169679                       # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total       335114                       # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1850088                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data      1826878                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total      3676966                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1999768                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data      1982892                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total      3982660                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data    150845515                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data    151067118                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total       301912633                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data    151041021                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data    151266098                       # number of overall hits
-system.cpu0.dcache.overall_hits::total      302307119                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      2645926                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data      2677151                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      5323077                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1113708                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1092396                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2206104                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       658322                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data       645499                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total      1303821                       # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data       625844                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data       606859                       # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total      1232703                       # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       150530                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data       156855                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total       307385                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            1                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      4385478                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      4376406                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       8761884                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      5043800                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      5021905                       # number of overall misses
-system.cpu0.dcache.overall_misses::total     10065705                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  42239397500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data  42446646000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  84686043500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  33748047000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  32757348500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  66505395500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  12855930500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data  12465111500                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total  25321042000                       # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   2217899500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data   2302924000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total   4520823500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        84500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        83000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       167500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  88843375000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  87669106000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 176512481000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  88843375000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  87669106000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 176512481000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data     80999258                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data     81068250                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total    162067508                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data     73440456                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data     73598736                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total    147039192                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       853828                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data       844479                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total      1698307                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       791279                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data       776538                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total      1567817                       # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2000618                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data      1983733                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total      3984351                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      1999769                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data      1982893                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total      3982662                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data    155230993                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data    155443524                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total    310674517                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data    156084821                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data    156288003                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total    312372824                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.032666                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033023                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.032845                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.015165                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.014843                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.015004                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.771024                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.764375                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.767718                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.790927                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data     0.781493                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total     0.786254                       # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.075242                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.079071                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.077148                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028251                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028154                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.028203                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.032314                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.032132                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.032223                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15963.937578                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15855.155723                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15909.227595                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30302.419485                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29986.697590                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30146.083548                       # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20541.749222                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20540.375112                       # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20541.072748                       # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14733.936757                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14681.865417                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14707.365356                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        84500                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        83000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        83750                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20258.538522                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20032.215018                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 20145.493937                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17614.373092                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17457.340591                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 17536.027630                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      7886218                       # number of writebacks
-system.cpu0.dcache.writebacks::total          7886218                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data        10945                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data        12188                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total        23133                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data         9895                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data        11343                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        21238                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data        35225                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data        35643                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total        70868                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data        20840                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data        23531                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total        44371                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data        20840                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data        23531                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total        44371                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      2634981                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data      2664963                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total      5299944                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1103813                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data      1081053                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total      2184866                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       657436                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data       644587                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total      1302023                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       625844                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data       606859                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total      1232703                       # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       115305                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data       121212                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total       236517                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      4364638                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data      4352875                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      8717513                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      5022074                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data      4997462                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total     10019536                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16630                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data        17075                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total        33705                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        15387                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data        18323                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        32017                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        35398                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total        67415                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  39320815000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data  39467824000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  78788639000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  32324995500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data  31332558500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  63657554000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  10585454000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  10489503500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  21074957500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  12230086500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11858252500                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  24088339000                       # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1546592000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1620640000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   3167232000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        83500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        82000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       165500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  83875897000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data  82658635000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 166534532000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  94461351000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data  93148138500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 187609489500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   6232781500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3103960000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   3128821500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   6232781500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.032531                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.032873                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.032702                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.015030                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.014688                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.014859                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.769986                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.763295                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.766659                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.790927                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.781493                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.786254                       # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.057635                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.061103                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059361                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028117                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028003                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028060                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.032175                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.031976                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032076                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14922.618038                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14809.895672                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14865.938017                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29284.847615                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28983.369456                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29135.678801                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16101.117067                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16273.216028                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16186.317369                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19541.749222                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19540.375112                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19541.072748                       # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13413.052339                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13370.293370                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13391.138903                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        83500                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        82000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        82750                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19217.148593                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18989.434569                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19103.445214                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18809.231206                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18639.088902                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18724.369023                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186648.226097                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183239.912152                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.569500                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96947.246775                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.781909                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92453.927168                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.tags.replacements         13794841                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.891071                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          880461329                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs         13795353                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            63.823037                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      31612122500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   239.271634                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   272.619438                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.467327                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.532460                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999787                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          217                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        908052045                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       908052045                       # Number of data accesses
-system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu0.icache.ReadReq_hits::cpu0.inst    440828036                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst    439633293                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      880461329                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst    440828036                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst    439633293                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       880461329                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst    440828036                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst    439633293                       # number of overall hits
-system.cpu0.icache.overall_hits::total      880461329                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst      6841683                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst      6953675                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total     13795358                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst      6841683                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst      6953675                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total      13795358                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst      6841683                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst      6953675                       # number of overall misses
-system.cpu0.icache.overall_misses::total     13795358                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  91946479500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst  93460380000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 185406859500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  91946479500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst  93460380000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 185406859500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  91946479500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst  93460380000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 185406859500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst    447669719                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst    446586968                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    894256687                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst    447669719                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst    446586968                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    894256687                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst    447669719                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst    446586968                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    894256687                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015283                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015571                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.015427                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015283                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015571                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.015427                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015283                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015571                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.015427                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13439.161022                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13440.429701                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13439.800511                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13439.800511                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13439.161022                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13440.429701                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13439.800511                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks     13794841                       # number of writebacks
-system.cpu0.icache.writebacks::total         13794841                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6841683                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst      6953675                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total     13795358                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst      6841683                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst      6953675                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total     13795358                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst      6841683                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst      6953675                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total     13795358                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  85104796500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst  86506705000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 171611501500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  85104796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst  86506705000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 171611501500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  85104796500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst  86506705000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 171611501500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   3263480000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   1959551500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst   1303928500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total   3263480000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.015427                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.015427                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.015283                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.015427                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12439.800511                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12439.161022                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12440.429701                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12439.800511                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551                       # average overall mshr uncacheable latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks                   132777                       # Table walker walks requested
-system.cpu1.dtb.walker.walksLong               132777                       # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        20416                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        96210                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore           14                       # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples       132763                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean     0.225967                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev    59.372165                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047       132761    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total       132763                       # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples       116640                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24809.139232                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21505.913100                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14394.407415                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767        77454     66.40%     66.40% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535        38152     32.71%     99.11% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303          546      0.47%     99.58% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071          345      0.30%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839            7      0.01%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607           46      0.04%     99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375            7      0.01%     99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143           32      0.03%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911           26      0.02%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679           11      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total       116640                       # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples  -4577799504                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean     0.827535                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev     0.377784                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0     -789509296     17.25%     17.25% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1    -3788290208     82.75%    100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total  -4577799504                       # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K        96210     82.49%     82.49% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M        20416     17.51%    100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total       116626                       # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       132777                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       132777                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       116626                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       116626                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total       249403                       # Table walker requests started/completed, data/inst
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    83913526                       # DTB read hits
-system.cpu1.dtb.read_misses                    101272                       # DTB read misses
-system.cpu1.dtb.write_hits                   76384029                       # DTB write hits
-system.cpu1.dtb.write_misses                    31505                       # DTB write misses
-system.cpu1.dtb.flush_tlb                       51822                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                   72847                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                  4726                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                    10026                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                84014798                       # DTB read accesses
-system.cpu1.dtb.write_accesses               76415534                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                        160297555                       # DTB hits
-system.cpu1.dtb.misses                         132777                       # DTB misses
-system.cpu1.dtb.accesses                    160430332                       # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
-system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
-system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
-system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
-system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
-system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
-system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
-system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
-system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
-system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
-system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
-system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
-system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
-system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
-system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
-system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks                    78422                       # Table walker walks requested
-system.cpu1.itb.walker.walksLong                78422                       # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2         4294                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3        68564                       # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples        78422                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0          78422    100.00%    100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total        78422                       # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples        72858                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 27889.977765                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24544.855352                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 16997.530464                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767        38730     53.16%     53.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535        32903     45.16%     98.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303          429      0.59%     98.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071          642      0.88%     99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839            9      0.01%     99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607           58      0.08%     99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375           14      0.02%     99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143           33      0.05%     99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911           12      0.02%     99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679            7      0.01%     99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447            5      0.01%     99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215            6      0.01%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519            3      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total        72858                       # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples   -850152296                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0     -850152296    100.00%    100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total   -850152296                       # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K        68564     94.11%     94.11% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M         4294      5.89%    100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total        72858                       # Table walker page sizes translated
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        78422                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total        78422                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        72858                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total        72858                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total       151280                       # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits                   446586968                       # ITB inst hits
-system.cpu1.itb.inst_misses                     78422                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                       51822                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid              21568                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                    527                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                   53690                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses               446665390                       # ITB inst accesses
-system.cpu1.itb.hits                        446586968                       # DTB hits
-system.cpu1.itb.misses                          78422                       # DTB misses
-system.cpu1.itb.accesses                    446665390                       # DTB accesses
-system.cpu1.numPwrStateTransitions              16158                       # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples         8079                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean    6172474015.634856                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev   126400173933.037643                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows         3542     43.84%     43.84% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10         4472     55.35%     99.20% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11            4      0.05%     99.24% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11           45      0.56%     99.80% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.83% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::overflows           12      0.15%    100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 5966386038488                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total           8079                       # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON   1953555674186                       # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 49867417572314                       # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles                     51820431949                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                  446306314                       # Number of instructions committed
-system.cpu1.committedOps                    524758442                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses            481884827                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                461371                       # Number of float alu accesses
-system.cpu1.num_func_calls                   26537022                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts     68126137                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                   481884827                       # number of integer instructions
-system.cpu1.num_fp_insts                       461371                       # number of float instructions
-system.cpu1.num_int_register_reads          702656955                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         382236658                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads              740777                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes             397264                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads           117187848                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes          116906080                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                    160291234                       # number of memory refs
-system.cpu1.num_load_insts                   83910548                       # Number of load instructions
-system.cpu1.num_store_insts                  76380686                       # Number of store instructions
-system.cpu1.num_idle_cycles              50237560488.814125                       # Number of idle cycles
-system.cpu1.num_busy_cycles              1582871460.185875                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.030545                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.969455                       # Percentage of idle cycles
-system.cpu1.Branches                         99714086                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu                363557209     69.24%     69.24% # Class of executed instruction
-system.cpu1.op_class::IntMult                 1101804      0.21%     69.45% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    48133      0.01%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  8      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                 13      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                 21      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.46% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc             57875      0.01%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.47% # Class of executed instruction
-system.cpu1.op_class::MemRead                83910548     15.98%     85.45% # Class of executed instruction
-system.cpu1.op_class::MemWrite               76380686     14.55%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                 525056297                       # Class of executed instruction
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq                40314                       # Transaction distribution
-system.iobus.trans_dist::ReadResp               40314                       # Transaction distribution
-system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
-system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230986                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total       230986                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  353770                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total      7334376                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  7492296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy             42149000                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy            25704500                       # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer24.occupancy            38608500                       # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy           568719305                       # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer3.occupancy           147746000                       # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements               115474                       # number of replacements
-system.iocache.tags.tagsinuse               10.457313                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs               115490                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         13153882422000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet     3.510792                       # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide     6.946521                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet     0.219424                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide     0.434158                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.653582                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses              1039794                       # Number of tag accesses
-system.iocache.tags.data_accesses             1039794                       # Number of data accesses
-system.iocache.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide         8829                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total             8866                       # number of ReadReq misses
-system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
-system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
-system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
-system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide       115493                       # number of demand (read+write) misses
-system.iocache.demand_misses::total            115533                       # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide       115493                       # number of overall misses
-system.iocache.overall_misses::total           115533                       # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet      5103000                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide   1592841262                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total   1597944262                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide  12773360043                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total  12773360043                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet      5454000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide  14366201305                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  14371655305                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet      5454000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide  14366201305                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  14371655305                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide         8829                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total           8866                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide       115493                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total          115533                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide       115493                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total         115533                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
-system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
-system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137918.918919                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 180410.155397                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 180232.829010                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119753.244234                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 119753.244234                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124394.374811                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet       136350                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124390.234083                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124394.374811                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         30355                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 3247                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     9.348630                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks          106630                       # number of writebacks
-system.iocache.writebacks::total               106630                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide         8829                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total         8866                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide       115493                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total       115533                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide       115493                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total       115533                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3253000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide   1151391262                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total   1154644262                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7433322678                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   7433322678                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet      3454000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   8584713940                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   8588167940                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet      3454000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   8584713940                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   8588167940                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87918.918919                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130410.155397                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 130232.829010                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69689.142335                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69689.142335                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        86350                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 74331.032530                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 74335.193754                       # average overall mshr miss latency
-system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.l2c.tags.replacements                  1313152                       # number of replacements
-system.l2c.tags.tagsinuse                65370.708254                       # Cycle average of tags in use
-system.l2c.tags.total_refs                   46163144                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                  1376667                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    33.532542                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               6637701500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   10009.384485                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker   223.831306                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker   257.129416                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3503.499374                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data    24340.454100                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker   220.642740                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker   259.400016                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2811.960142                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data    23744.406675                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.152731                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.003415                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.003923                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.053459                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.371406                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.003367                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.003958                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042907                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.362311                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.997478                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023          266                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        63249                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4          266                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          805                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         5995                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56179                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.004059                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.965103                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                392950064                       # Number of tag accesses
-system.l2c.tags.data_accesses               392950064                       # Number of data accesses
-system.l2c.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.l2c.ReadReq_hits::cpu0.dtb.walker       228515                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker       155195                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker       232922                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker       157807                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 774439                       # number of ReadReq hits
-system.l2c.WritebackDirty_hits::writebacks      7886218                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         7886218                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks     13793267                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total        13793267                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data           13066                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data           13135                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total               26201                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           823252                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data           809118                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total              1632370                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst       6801903                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst       6913178                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total          13715081                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data      3265618                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data      3290649                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          6556267                       # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data       366070                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data       355034                       # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total           721104                       # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker        228515                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker        155195                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst             6801903                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data             4088870                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker        232922                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker        157807                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst             6913178                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data             4099767                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                22678157                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker       228515                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker       155195                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst            6801903                       # number of overall hits
-system.l2c.overall_hits::cpu0.data            4088870                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker       232922                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker       157807                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst            6913178                       # number of overall hits
-system.l2c.overall_hits::cpu1.data            4099767                       # number of overall hits
-system.l2c.overall_hits::total               22678157                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker         1963                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker         2098                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker         2348                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker         2153                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 8562                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1921                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1961                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3882                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         265574                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data         256839                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             522413                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst        39780                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst        40497                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           80277                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data       142104                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data       140113                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total         282217                       # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data       259774                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data       251825                       # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total         511599                       # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker         1963                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker         2098                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst             39780                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            407678                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker         2348                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker         2153                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst             40497                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data            396952                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                893469                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker         1963                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker         2098                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst            39780                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           407678                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker         2348                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker         2153                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst            40497                       # number of overall misses
-system.l2c.overall_misses::cpu1.data           396952                       # number of overall misses
-system.l2c.overall_misses::total               893469                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker    171313500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker    185909000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker    205293000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker    189294000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      751809500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     32649000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     35540500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     68189500                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data        82000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data        80500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       162500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data  21807133500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data  20994818000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  42801951500                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu0.inst   3285719000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst   3349644500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total   6635363500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu0.data  12013468000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data  11840561500                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total  23854029500                       # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu0.data        57000                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data       397500                       # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total       454500                       # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker    171313500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker    185909000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst   3285719000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  33820601500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker    205293000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker    189294000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst   3349644500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data  32835379500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     74043154000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker    171313500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker    185909000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst   3285719000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  33820601500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker    205293000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker    189294000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst   3349644500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data  32835379500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    74043154000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker       230478                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker       157293                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker       235270                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker       159960                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             783001                       # number of ReadReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      7886218                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      7886218                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks     13793267                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total     13793267                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data        14987                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data        15096                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           30083                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data      1088826                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data      1065957                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total          2154783                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst      6841683                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst      6953675                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total      13795358                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data      3407722                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data      3430762                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      6838484                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data       625844                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data       606859                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total      1232703                       # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker       230478                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker       157293                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst         6841683                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         4496548                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker       235270                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker       159960                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst         6953675                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data         4496719                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total            23571626                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker       230478                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker       157293                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst        6841683                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        4496548                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker       235270                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker       159960                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst        6953675                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data        4496719                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total           23571626                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.010935                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.128178                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.129902                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.129043                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.243909                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.240947                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.242443                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.005814                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.005824                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.005819                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.041701                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.040840                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.041269                       # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data     0.415078                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data     0.414965                       # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total     0.415022                       # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.005814                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.090665                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005824                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.088276                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.037904                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.008517                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.013338                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.005814                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.090665                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.009980                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.013460                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005824                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.088276                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.037904                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 87807.696800                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16995.835502                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18123.661397                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 17565.558990                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data        82000                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data        80500                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total        81250                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82113.209501                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81743.107550                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 81931.252668                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82597.259930                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82713.398523                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 82655.847877                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84539.970726                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84507.229879                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 84523.715793                       # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu0.data     0.219421                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data     1.578477                       # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total     0.888391                       # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 82597.259930                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 82959.103753                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 82713.398523                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 82718.765745                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 82871.542270                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87271.268467                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88612.488084                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 82597.259930                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 82959.103753                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87433.134583                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87921.040409                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 82713.398523                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 82718.765745                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 82871.542270                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks             1124258                       # number of writebacks
-system.l2c.writebacks::total                  1124258                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker         1963                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker         2098                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker         2348                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker         2153                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            8562                       # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1921                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1961                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3882                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       265574                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data       256839                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        522413                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu0.inst        39780                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst        40497                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total        80277                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu0.data       142104                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data       140113                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total       282217                       # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu0.data       259774                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data       251825                       # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total       511599                       # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker         1963                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker         2098                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        39780                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       407678                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker         2348                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker         2153                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst        40497                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data       396952                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           893469                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker         1963                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker         2098                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        39780                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       407678                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker         2348                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker         2153                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst        40497                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data       396952                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          893469                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        25924                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16630                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.inst        17201                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data        17075                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total        76830                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu0.data        15387                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data        18323                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        25924                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu0.data        32017                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.inst        17201                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data        35398                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       110540                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    666189500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     36648500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     37294000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     73942500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        72000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data        70500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total       142500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data  19151393500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data  18426428000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total  37577821500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst   2887919000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst   2944674500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total   5832593500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  10592406543                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  10439412039                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total  21031818582                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data   4849839500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   4701857000                       # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total   9551696500                       # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst   2887919000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  29743800043                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst   2944674500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data  28865840039                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  65108423082                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    151683500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    164929000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst   2887919000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  29743800043                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    181813000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    167764000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst   2944674500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data  28865840039                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  65108423082                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2895695500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   2915001000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   8535114000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1635501500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2895695500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst   1088916000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   2915001000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   8535114000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.010935                       # mshr miss rate for ReadReq accesses
-system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.128178                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.129902                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.129043                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.243909                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.240947                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.242443                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005819                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.041701                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.040840                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.041269                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.415078                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.414965                       # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total     0.415022                       # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.037904                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.008517                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.013338                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.005814                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.090665                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.009980                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.013460                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005824                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.088276                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.037904                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77807.696800                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19077.824050                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19017.848037                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19047.527048                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        72000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        70500                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72113.209501                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71743.107550                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 71931.252668                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72655.847877                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74539.819731                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74507.090984                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74523.570805                       # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18669.456913                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18671.128760                       # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.279848                       # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72597.259930                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72959.051121                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72713.398523                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72718.716719                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 72871.496473                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174124.804570                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170717.481698                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111090.901991                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 90442.436830                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 82349.313521                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77212.900308                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests       2952008                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests      1460758                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         3777                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq               76830                       # Transaction distribution
-system.membus.trans_dist::ReadResp             456752                       # Transaction distribution
-system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
-system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1230888                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           196616                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4451                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            521854                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           521854                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        379922                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq        618256                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         6940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      3704616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      3834318                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       236933                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       236933                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4071251                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        13880                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    129250016                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total    129419862                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7203584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      7203584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               136623446                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                             3602                       # Total snoops (count)
-system.membus.snoopTraffic                     230016                       # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples           1635025                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.019925                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.139743                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1602447     98.01%     98.01% # Request fanout histogram
-system.membus.snoop_fanout::1                   32578      1.99%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             1635025                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           106891500                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             5673000                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy          8054295189                       # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         4944826036                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer3.occupancy           44675477                       # Layer occupancy (ticks)
-system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
-system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
-system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
-system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
-system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
-system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
-system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets                 3                       # Total Packets
-system.realview.ethernet.totBytes                 966                       # Total Bytes
-system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts           18                       # number of posts to CPU
-system.realview.ethernet.droppedPackets             0                       # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
-system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
-system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
-system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests     48651794                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests     24630474                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1743                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops           2027                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops         2027                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820973246500                       # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq            1286860                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp          21921577                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             33710                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            33710                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      9010476                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean     13794841                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict         2528106                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           30086                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          30088                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq          2154783                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp         2154783                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq      13795358                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      6841623                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq      1261461                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp      1232703                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side     41471807                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     30873248                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side       776442                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      1216589                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              74338086                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side   1765945236                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side   1080533506                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side      2538024                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side      3725984                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total             2852742750                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                         1772959                       # Total snoops (count)
-system.toL2Bus.snoopTraffic                  75424744                       # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples         26717035                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.021855                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.146208                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0               26133147     97.81%     97.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                 583888      2.19%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total           26717035                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy        46394041000                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1620386                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy       20736162000                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy       14171869470                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy         459189000                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         750841000                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
deleted file mode 100644 (file)
index d74b75b..0000000
+++ /dev/null
@@ -1,183 +0,0 @@
-[    0.000000] Initializing cgroup subsys cpu\r
-[    0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014\r
-[    0.000000] CPU: AArch64 Processor [410fc0f0] revision 0\r
-[    0.000000] No Cache Writeback Granule information, assuming cache line size 64\r
-[    0.000000] Memory limited to 256MB\r
-[    0.000000] cma: CMA: reserved 16 MiB at 8f000000\r
-[    0.000000] On node 0 totalpages: 65536\r
-[    0.000000]   DMA zone: 896 pages used for memmap\r
-[    0.000000]   DMA zone: 0 pages reserved\r
-[    0.000000]   DMA zone: 65536 pages, LIFO batch:15\r
-[    0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056\r
-[    0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096\r
-[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 \r
-[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 64640\r
-[    0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1\r
-[    0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)\r
-[    0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)\r
-[    0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-[    0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)\r
-[    0.000000] Virtual kernel memory layout:\r
-[    0.000000]     vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000   (245759 MB)\r
-[    0.000000]     vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000   (     3 MB)\r
-[    0.000000]     modules : 0xffffffbffc000000 - 0xffffffc000000000   (    64 MB)\r
-[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc010000000   (   256 MB)\r
-[    0.000000]       .init : 0xffffffc000692000 - 0xffffffc0006c6200   (   209 kB)\r
-[    0.000000]       .text : 0xffffffc000080000 - 0xffffffc0006914e4   (  6214 kB)\r
-[    0.000000]       .data : 0xffffffc0006c7000 - 0xffffffc0007141e0   (   309 kB)\r
-[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1\r
-[    0.000000] Preemptible hierarchical RCU implementation.\r
-[    0.000000]         RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.\r
-[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
-[    0.000000] NR_IRQS:64 nr_irqs:64 0\r
-[    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[    0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[    0.000039] Console: colour dummy device 80x25\r
-[    0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[    0.000044] pid_max: default: 32768 minimum: 301\r
-[    0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000067] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[    0.000247] hw perfevents: no hardware support available\r
-[    1.060141] CPU1: failed to come online\r
-[    2.080278] CPU2: failed to come online\r
-[    3.100415] CPU3: failed to come online\r
-[    3.100420] Brought up 1 CPUs\r
-[    3.100422] SMP: Total of 1 processors activated.\r
-[    3.100519] devtmpfs: initialized\r
-[    3.101579] atomic64_test: passed\r
-[    3.101653] regulator-dummy: no parameters\r
-[    3.102392] NET: Registered protocol family 16\r
-[    3.102653] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[    3.102663] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[    3.103271] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[    3.103277] Serial: AMBA PL011 UART driver\r
-[    3.103628] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[    3.103692] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[    3.104278] console [ttyAMA0] enabled\r
-[    3.104379] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[    3.104429] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[    3.104479] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[    3.104525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[    3.131020] 3V3: 3300 mV \r
-[    3.131093] vgaarb: loaded\r
-[    3.131183] SCSI subsystem initialized\r
-[    3.131252] libata version 3.00 loaded.\r
-[    3.131332] usbcore: registered new interface driver usbfs\r
-[    3.131358] usbcore: registered new interface driver hub\r
-[    3.131413] usbcore: registered new device driver usb\r
-[    3.131456] pps_core: LinuxPPS API ver. 1 registered\r
-[    3.131466] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[    3.131488] PTP clock support registered\r
-[    3.131706] Switched to clocksource arch_sys_counter\r
-[    3.133706] NET: Registered protocol family 2\r
-[    3.133856] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[    3.133884] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[    3.133918] TCP: Hash tables configured (established 2048 bind 2048)\r
-[    3.133940] TCP: reno registered\r
-[    3.133948] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.133966] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[    3.134029] NET: Registered protocol family 1\r
-[    3.134094] RPC: Registered named UNIX socket transport module.\r
-[    3.134105] RPC: Registered udp transport module.\r
-[    3.134113] RPC: Registered tcp transport module.\r
-[    3.134122] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[    3.134136] PCI: CLS 0 bytes, default 64\r
-[    3.134445] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[    3.134644] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[    3.138048] fuse init (API version 7.23)\r
-[    3.138207] msgmni has been set to 469\r
-[    3.142619] io scheduler noop registered\r
-[    3.142717] io scheduler cfq registered (default)\r
-[    3.143500] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[    3.143514] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]\r
-[    3.143527] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[    3.143541] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[    3.143553] pci_bus 0000:00: scanning bus\r
-[    3.143566] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[    3.143581] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[    3.143598] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.143658] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[    3.143672] pci 0000:00:01.0: reg 0x10: [io  0x0000-0x0007]\r
-[    3.143684] pci 0000:00:01.0: reg 0x14: [io  0x0000-0x0003]\r
-[    3.143697] pci 0000:00:01.0: reg 0x18: [io  0x0000-0x0007]\r
-[    3.143710] pci 0000:00:01.0: reg 0x1c: [io  0x0000-0x0003]\r
-[    3.143722] pci 0000:00:01.0: reg 0x20: [io  0x0000-0x000f]\r
-[    3.143736] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[    3.143793] pci_bus 0000:00: fixups for bus\r
-[    3.143803] pci_bus 0000:00: bus scan returning with max=00\r
-[    3.143817] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[    3.143842] pci 0000:00:00.0: fixup irq: got 33\r
-[    3.143852] pci 0000:00:00.0: assigning IRQ 33\r
-[    3.143866] pci 0000:00:01.0: fixup irq: got 34\r
-[    3.143875] pci 0000:00:01.0: assigning IRQ 34\r
-[    3.143889] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[    3.143904] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[    3.143919] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[    3.143933] pci 0000:00:01.0: BAR 4: assigned [io  0x1000-0x100f]\r
-[    3.143946] pci 0000:00:01.0: BAR 0: assigned [io  0x1010-0x1017]\r
-[    3.143960] pci 0000:00:01.0: BAR 2: assigned [io  0x1018-0x101f]\r
-[    3.143973] pci 0000:00:01.0: BAR 1: assigned [io  0x1020-0x1023]\r
-[    3.143986] pci 0000:00:01.0: BAR 3: assigned [io  0x1024-0x1027]\r
-[    3.144848] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[    3.145335] ata_piix 0000:00:01.0: version 2.13\r
-[    3.145347] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[    3.145377] ata_piix 0000:00:01.0: enabling bus mastering\r
-[    3.145943] scsi0 : ata_piix\r
-[    3.146120] scsi1 : ata_piix\r
-[    3.146172] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[    3.146185] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[    3.146369] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[    3.146383] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[    3.146404] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[    3.146418] e1000 0000:00:00.0: enabling bus mastering\r
-[    3.301739] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[    3.301750] ata1.00: 2096640 sectors, multi 0: LBA \r
-[    3.301784] ata1.00: configured for UDMA/33\r
-[    3.301855] scsi 0:0:0:0: Direct-Access     ATA      M5 IDE Disk      n/a  PQ: 0 ANSI: 5\r
-[    3.302047] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[    3.302082] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[    3.302139] sd 0:0:0:0: [sda] Write Protect is off\r
-[    3.302150] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[    3.302179] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[    3.302375]  sda: sda1\r
-[    3.302573] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[    3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[    3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[    3.422104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[    3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[    3.422145] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[    3.422158] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[    3.422288] usbcore: registered new interface driver usb-storage\r
-[    3.422377] mousedev: PS/2 mouse device common for all mice\r
-[    3.422663] usbcore: registered new interface driver usbhid\r
-[    3.422673] usbhid: USB HID core driver\r
-[    3.422723] TCP: cubic registered\r
-[    3.422732] NET: Registered protocol family 17\r
-\0[    3.423311] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[    3.423356] devtmpfs: mounted\r
-[    3.423405] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
-\0\0\rINIT: \0version 2.88 booting\0\r\r
-\0Starting udev\r
-[    3.470207] udevd[607]: starting version 182\r
-Starting Bootlog daemon: bootlogd.\r\r
-[    3.606569] random: dd urandom read with 21 bits of entropy available\r
-Populating dev cache\r\r
-net.ipv4.conf.default.rp_filter = 1\r\r
-net.ipv4.conf.all.rp_filter = 1\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-Mon Jan 27 08:00:00 UTC 2014\r\r
-hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
-\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... [    3.791940] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
-udhcpc (v1.21.1) started\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-Sending discover...\r\r
-No lease, forking to background\r\r
-done.\r\r
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6\r\r\r
-rpcbind: cannot create socket for tcp6\r\r\r
-done.\r\r
-rpcbind: cannot get uid of '': Success\r\r\r
-creating NFS state directory: done\r\r
-starting statd: done\r\r
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/EMPTY
new file mode 100644 (file)
index 0000000..e69de29
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
deleted file mode 100644 (file)
index bf97d6d..0000000
+++ /dev/null
@@ -1,1990 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=true
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain dvfs_handler e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-eventq_index=0
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
-kernel_addr_check=true
-load_addr_mask=18446744073709551615
-load_offset=0
-mem_mode=atomic
-mem_ranges=0:134217727
-memories=system.physmem
-mmap_using_noreserve=false
-multi_thread=false
-num_work_ids=16
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-eventq_index=0
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-eventq_index=0
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.apicbridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-master=system.membus.slave[0]
-slave=system.iobus.master[0]
-
-[system.bridge]
-type=Bridge
-clk_domain=system.clk_domain
-delay=50000
-eventq_index=0
-ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
-req_size=16
-resp_size=16
-master=system.iobus.slave[0]
-slave=system.membus.master[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-eventq_index=0
-fastmem=false
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-simulate_data_stalls=false
-simulate_inst_stalls=false
-socket_id=0
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=
-dcache_port=system.cpu0.dcache.cpu_side
-icache_port=system.cpu0.icache.cpu_side
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-
-[system.cpu0.dcache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=4
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=false
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.dcache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=false
-cpu_side=system.cpu0.dcache_port
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu0.dcache.tags]
-type=LRU
-assoc=4
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.toL2Bus.slave[3]
-
-[system.cpu0.icache]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=1
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_read_only=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=32768
-system=system
-tags=system.cpu0.icache.tags
-tgts_per_mshr=20
-write_buffers=8
-writeback_clean=true
-cpu_side=system.cpu0.icache_port
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu0.icache.tags]
-type=LRU
-assoc=1
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=32768
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-eventq_index=0
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.membus.slave[3]
-int_slave=system.membus.master[2]
-pio=system.membus.master[1]
-
-[system.cpu0.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-port=system.toL2Bus.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=dtb isa itb tracer
-branchPred=Null
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-eventq_index=0
-function_trace=false
-function_trace_start=0
-interrupts=
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-switched_out=true
-system=system
-tracer=system.cpu1.tracer
-workload=
-
-[system.cpu1.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu1.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu1.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu1.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu2]
-type=DerivO3CPU
-children=branchPred dtb fuPool isa itb tracer
-LFSTSize=1024
-LQEntries=32
-LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-branchPred=system.cpu2.branchPred
-cachePorts=200
-checker=Null
-clk_domain=system.cpu_clk_domain
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-cpu_id=0
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-eventq_index=0
-fetchBufferSize=64
-fetchQueueSize=32
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu2.fuPool
-function_trace=false
-function_trace_start=0
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-interrupts=
-isa=system.cpu2.isa
-issueToExecuteDelay=1
-issueWidth=8
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-needsTSO=true
-numIQEntries=64
-numPhysCCRegs=1280
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-profile=0
-progress_interval=0
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-simpoint_start_insts=
-smtCommitPolicy=RoundRobin
-smtFetchPolicy=SingleThread
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtNumFetchingThreads=1
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-socket_id=0
-squashWidth=8
-store_set_clear_period=250000
-switched_out=true
-system=system
-tracer=system.cpu2.tracer
-trapLatency=13
-wbWidth=8
-workload=
-
-[system.cpu2.branchPred]
-type=TournamentBP
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-
-[system.cpu2.dtb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu2.dtb.walker
-
-[system.cpu2.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu2.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
-eventq_index=0
-
-[system.cpu2.fuPool.FUList0]
-type=FUDesc
-children=opList
-count=6
-eventq_index=0
-opList=system.cpu2.fuPool.FUList0.opList
-
-[system.cpu2.fuPool.FUList0.opList]
-type=OpDesc
-eventq_index=0
-opClass=IntAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-eventq_index=0
-opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
-
-[system.cpu2.fuPool.FUList1.opList0]
-type=OpDesc
-eventq_index=0
-opClass=IntMult
-opLat=3
-pipelined=true
-
-[system.cpu2.fuPool.FUList1.opList1]
-type=OpDesc
-eventq_index=0
-opClass=IntDiv
-opLat=1
-pipelined=false
-
-[system.cpu2.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
-
-[system.cpu2.fuPool.FUList2.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatAdd
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList2.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatCmp
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList2.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatCvt
-opLat=2
-pipelined=true
-
-[system.cpu2.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
-
-[system.cpu2.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-opClass=FloatMult
-opLat=4
-pipelined=true
-
-[system.cpu2.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-opClass=FloatDiv
-opLat=12
-pipelined=false
-
-[system.cpu2.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-opClass=FloatSqrt
-opLat=24
-pipelined=false
-
-[system.cpu2.fuPool.FUList4]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu2.fuPool.FUList4.opList
-
-[system.cpu2.fuPool.FUList4.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5]
-type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
-
-[system.cpu2.fuPool.FUList5.opList00]
-type=OpDesc
-eventq_index=0
-opClass=SimdAdd
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList01]
-type=OpDesc
-eventq_index=0
-opClass=SimdAddAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList02]
-type=OpDesc
-eventq_index=0
-opClass=SimdAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList03]
-type=OpDesc
-eventq_index=0
-opClass=SimdCmp
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList04]
-type=OpDesc
-eventq_index=0
-opClass=SimdCvt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList05]
-type=OpDesc
-eventq_index=0
-opClass=SimdMisc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList06]
-type=OpDesc
-eventq_index=0
-opClass=SimdMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList07]
-type=OpDesc
-eventq_index=0
-opClass=SimdMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList08]
-type=OpDesc
-eventq_index=0
-opClass=SimdShift
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList09]
-type=OpDesc
-eventq_index=0
-opClass=SimdShiftAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList10]
-type=OpDesc
-eventq_index=0
-opClass=SimdSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList11]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAdd
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList12]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatAlu
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList13]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCmp
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList14]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatCvt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList15]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatDiv
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList16]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMisc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList17]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMult
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList18]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatMultAcc
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList5.opList19]
-type=OpDesc
-eventq_index=0
-opClass=SimdFloatSqrt
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu2.fuPool.FUList6.opList
-
-[system.cpu2.fuPool.FUList6.opList]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
-eventq_index=0
-opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
-
-[system.cpu2.fuPool.FUList7.opList0]
-type=OpDesc
-eventq_index=0
-opClass=MemRead
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList7.opList1]
-type=OpDesc
-eventq_index=0
-opClass=MemWrite
-opLat=1
-pipelined=true
-
-[system.cpu2.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
-eventq_index=0
-opList=system.cpu2.fuPool.FUList8.opList
-
-[system.cpu2.fuPool.FUList8.opList]
-type=OpDesc
-eventq_index=0
-opClass=IprAccess
-opLat=3
-pipelined=false
-
-[system.cpu2.isa]
-type=X86ISA
-eventq_index=0
-
-[system.cpu2.itb]
-type=X86TLB
-children=walker
-eventq_index=0
-size=64
-walker=system.cpu2.itb.walker
-
-[system.cpu2.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-num_squash_per_cycle=4
-system=system
-
-[system.cpu2.tracer]
-type=ExeTracer
-eventq_index=0
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.dvfs_handler]
-type=DVFSHandler
-domains=
-enable=false
-eventq_index=0
-sys_clk_domain=system.clk_domain
-transition_latency=100000000
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3 entries4
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4
-eventq_index=0
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-eventq_index=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-eventq_index=0
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-eventq_index=0
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=134217728
-eventq_index=0
-range_type=2
-size=3087007744
-
-[system.e820_table.entries4]
-type=X86E820Entry
-addr=4294901760
-eventq_index=0
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-eventq_index=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
-eventq_index=0
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-eventq_index=0
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-eventq_index=0
-id=1
-version=17
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPBus
-bus_id=0
-bus_type=PCI
-eventq_index=0
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=1
-bus_type=ISA
-eventq_index=0
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=16
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=2
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=1
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=3
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=4
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=5
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=6
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=7
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=8
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=9
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=10
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=11
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=12
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=13
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=0
-eventq_index=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=1
-dest_io_apic_intin=14
-eventq_index=0
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=1
-eventq_index=0
-parent_bus=0
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-eventq_index=0
-sys=system
-
-[system.iobus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=1
-frontend_latency=2
-response_latency=2
-use_default_range=false
-width=16
-default=system.pc.pci_host.pio
-master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
-slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
-
-[system.iocache]
-type=Cache
-children=tags
-addr_ranges=0:134217727
-assoc=8
-clk_domain=system.clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=false
-hit_latency=50
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=50
-sequential_access=false
-size=1024
-system=system
-tags=system.iocache.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.iobus.master[18]
-mem_side=system.membus.slave[4]
-
-[system.iocache.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-hit_latency=50
-sequential_access=false
-size=1024
-
-[system.l2c]
-type=Cache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=8
-clk_domain=system.cpu_clk_domain
-clusivity=mostly_incl
-demand_mshr_reserve=1
-eventq_index=0
-forward_snoops=true
-hit_latency=20
-is_read_only=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-sequential_access=false
-size=4194304
-system=system
-tags=system.l2c.tags
-tgts_per_mshr=12
-write_buffers=8
-writeback_clean=false
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
-
-[system.l2c.tags]
-type=LRU
-assoc=8
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=20
-sequential_access=false
-size=4194304
-
-[system.membus]
-type=CoherentXBar
-children=badaddr_responder
-clk_domain=system.clk_domain
-eventq_index=0
-forward_latency=4
-frontend_latency=3
-response_latency=2
-snoop_filter=Null
-snoop_response_latency=4
-system=system
-use_default_range=false
-width=16
-default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
-slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
-
-[system.membus.badaddr_responder]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=0
-pio_latency=100000
-pio_size=8
-ret_bad_addr=true
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.membus.default
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge
-eventq_index=0
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[12]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.iobus.master[13]
-
-[system.pc.com_1.terminal]
-type=Terminal
-eventq_index=0
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[14]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[15]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[16]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[17]
-
-[system.pc.i_dont_exist1]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[10]
-
-[system.pc.i_dont_exist2]
-type=IsaFake
-clk_domain=system.clk_domain
-eventq_index=0
-fake_mem=false
-pio_addr=9223372036854776045
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.iobus.master[11]
-
-[system.pc.pci_host]
-type=GenericPciHost
-clk_domain=system.clk_domain
-conf_base=13835058055282163712
-conf_device_bits=8
-conf_size=16777216
-eventq_index=0
-pci_dma_base=0
-pci_mem_base=0
-pci_pio_base=9223372036854775808
-platform=system.pc
-system=system
-pio=system.iobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-eventq_index=0
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan  1 00:00:00 2012
-pio=system.iobus.master[1]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-eventq_index=0
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.iobus.master[2]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CapabilityPtr=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-LegacyIOBase=9223372036854775808
-MSICAPBaseOffset=0
-MSICAPCapId=0
-MSICAPMaskBits=0
-MSICAPMsgAddr=0
-MSICAPMsgCtrl=0
-MSICAPMsgData=0
-MSICAPMsgUpperAddr=0
-MSICAPNextCapability=0
-MSICAPPendingBits=0
-MSIXCAPBaseOffset=0
-MSIXCAPCapId=0
-MSIXCAPNextCapability=0
-MSIXMsgCtrl=0
-MSIXPbaOffset=0
-MSIXTableOffset=0
-MaximumLatency=0
-MinimumGrant=0
-PMCAPBaseOffset=0
-PMCAPCapId=0
-PMCAPCapabilities=0
-PMCAPCtrlStatus=0
-PMCAPNextCapability=0
-PXCAPBaseOffset=0
-PXCAPCapId=0
-PXCAPCapabilities=0
-PXCAPDevCap2=0
-PXCAPDevCapabilities=0
-PXCAPDevCtrl=0
-PXCAPDevCtrl2=0
-PXCAPDevStatus=0
-PXCAPLinkCap=0
-PXCAPLinkCtrl=0
-PXCAPLinkStatus=0
-PXCAPNextCapability=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-eventq_index=0
-host=system.pc.pci_host
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-system=system
-dma=system.iobus.slave[1]
-pio=system.iobus.master[3]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-eventq_index=0
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-eventq_index=0
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-eventq_index=0
-image_file=/work/gem5/dist/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-eventq_index=0
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-eventq_index=0
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-eventq_index=0
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=1
-clk_domain=system.clk_domain
-eventq_index=0
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.iobus.slave[2]
-pio=system.iobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-eventq_index=0
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.iobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.iobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-eventq_index=0
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.iobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-eventq_index=0
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.iobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-eventq_index=0
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-eventq_index=0
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.iobus.master[8]
-
-[system.physmem]
-type=DRAMCtrl
-IDD0=0.075000
-IDD02=0.000000
-IDD2N=0.050000
-IDD2N2=0.000000
-IDD2P0=0.000000
-IDD2P02=0.000000
-IDD2P1=0.000000
-IDD2P12=0.000000
-IDD3N=0.057000
-IDD3N2=0.000000
-IDD3P0=0.000000
-IDD3P02=0.000000
-IDD3P1=0.000000
-IDD3P12=0.000000
-IDD4R=0.187000
-IDD4R2=0.000000
-IDD4W=0.165000
-IDD4W2=0.000000
-IDD5=0.220000
-IDD52=0.000000
-IDD6=0.000000
-IDD62=0.000000
-VDD=1.500000
-VDD2=0.000000
-activation_limit=4
-addr_mapping=RoRaBaCoCh
-bank_groups_per_rank=0
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-device_size=536870912
-devices_per_rank=8
-dll=true
-eventq_index=0
-in_addr_map=true
-max_accesses_per_row=16
-mem_sched_policy=frfcfs
-min_writes_per_switch=16
-null=false
-page_policy=open_adaptive
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCCD_L=0
-tCK=1250
-tCL=13750
-tCS=2500
-tRAS=35000
-tRCD=13750
-tREFI=7800000
-tRFC=260000
-tRP=13750
-tRRD=6000
-tRRD_L=0
-tRTP=7500
-tRTW=2500
-tWR=15000
-tWTR=7500
-tXAW=30000
-tXP=0
-tXPDLL=0
-tXS=0
-tXSDLL=0
-write_buffer_size=64
-write_high_thresh_perc=85
-write_low_thresh_perc=50
-port=system.membus.master[3]
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-eventq_index=0
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-eventq_index=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.toL2Bus]
-type=CoherentXBar
-children=snoop_filter
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_latency=0
-frontend_latency=1
-response_latency=1
-snoop_filter=system.toL2Bus.snoop_filter
-snoop_response_latency=1
-system=system
-use_default_range=false
-width=32
-master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.toL2Bus.snoop_filter]
-type=SnoopFilter
-eventq_index=0
-lookup_latency=0
-max_capacity=8388608
-system=system
-
-[system.voltage_domain]
-type=VoltageDomain
-eventq_index=0
-voltage=1.000000
-
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
deleted file mode 100644 (file)
index aed66fc..0000000
+++ /dev/null
@@ -1,2677 +0,0 @@
-{
-    "name": null, 
-    "sim_quantum": 0, 
-    "system": {
-        "kernel": "/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9", 
-        "mmap_using_noreserve": false, 
-        "kernel_addr_check": true, 
-        "bridge": {
-            "ranges": [
-                "3221225472:4294901760", 
-                "9223372036854775808:11529215046068469759", 
-                "13835058055282163712:18446744073709551615"
-            ], 
-            "slave": {
-                "peer": "system.membus.master[0]", 
-                "role": "SLAVE"
-            }, 
-            "name": "bridge", 
-            "req_size": 16, 
-            "clk_domain": "system.clk_domain", 
-            "delay": 50000, 
-            "eventq_index": 0, 
-            "master": {
-                "peer": "system.iobus.slave[0]", 
-                "role": "MASTER"
-            }, 
-            "cxx_class": "Bridge", 
-            "path": "system.bridge", 
-            "resp_size": 16, 
-            "type": "Bridge"
-        }, 
-        "iobus": {
-            "slave": {
-                "peer": [
-                    "system.bridge.master", 
-                    "system.pc.south_bridge.ide.dma", 
-                    "system.pc.south_bridge.io_apic.int_master"
-                ], 
-                "role": "SLAVE"
-            }, 
-            "name": "iobus", 
-            "default": {
-                "peer": "system.pc.pci_host.pio", 
-                "role": "MASTER"
-            }, 
-            "forward_latency": 1, 
-            "clk_domain": "system.clk_domain", 
-            "width": 16, 
-            "eventq_index": 0, 
-            "master": {
-                "peer": [
-                    "system.apicbridge.slave", 
-                    "system.pc.south_bridge.cmos.pio", 
-                    "system.pc.south_bridge.dma1.pio", 
-                    "system.pc.south_bridge.ide.pio", 
-                    "system.pc.south_bridge.keyboard.pio", 
-                    "system.pc.south_bridge.pic1.pio", 
-                    "system.pc.south_bridge.pic2.pio", 
-                    "system.pc.south_bridge.pit.pio", 
-                    "system.pc.south_bridge.speaker.pio", 
-                    "system.pc.south_bridge.io_apic.pio", 
-                    "system.pc.i_dont_exist1.pio", 
-                    "system.pc.i_dont_exist2.pio", 
-                    "system.pc.behind_pci.pio", 
-                    "system.pc.com_1.pio", 
-                    "system.pc.fake_com_2.pio", 
-                    "system.pc.fake_com_3.pio", 
-                    "system.pc.fake_com_4.pio", 
-                    "system.pc.fake_floppy.pio", 
-                    "system.iocache.cpu_side"
-                ], 
-                "role": "MASTER"
-            }, 
-            "response_latency": 2, 
-            "cxx_class": "NoncoherentXBar", 
-            "path": "system.iobus", 
-            "type": "NoncoherentXBar", 
-            "use_default_range": false, 
-            "frontend_latency": 2
-        }, 
-        "apicbridge": {
-            "ranges": [
-                "11529215046068469760:11529215046068473855"
-            ], 
-            "slave": {
-                "peer": "system.iobus.master[0]", 
-                "role": "SLAVE"
-            }, 
-            "name": "apicbridge", 
-            "req_size": 16, 
-            "clk_domain": "system.clk_domain", 
-            "delay": 50000, 
-            "eventq_index": 0, 
-            "master": {
-                "peer": "system.membus.slave[0]", 
-                "role": "MASTER"
-            }, 
-            "cxx_class": "Bridge", 
-            "path": "system.apicbridge", 
-            "resp_size": 16, 
-            "type": "Bridge"
-        }, 
-        "symbolfile": "", 
-        "l2c": {
-            "cpu_side": {
-                "peer": "system.toL2Bus.master[0]", 
-                "role": "SLAVE"
-            }, 
-            "clusivity": "mostly_incl", 
-            "prefetcher": null, 
-            "clk_domain": "system.cpu_clk_domain", 
-            "write_buffers": 8, 
-            "response_latency": 20, 
-            "cxx_class": "Cache", 
-            "size": 4194304, 
-            "tags": {
-                "name": "tags", 
-                "eventq_index": 0, 
-                "hit_latency": 20, 
-                "clk_domain": "system.cpu_clk_domain", 
-                "sequential_access": false, 
-                "assoc": 8, 
-                "cxx_class": "LRU", 
-                "path": "system.l2c.tags", 
-                "block_size": 64, 
-                "type": "LRU", 
-                "size": 4194304
-            }, 
-            "system": "system", 
-            "max_miss_count": 0, 
-            "eventq_index": 0, 
-            "mem_side": {
-                "peer": "system.membus.slave[2]", 
-                "role": "MASTER"
-            }, 
-            "type": "Cache", 
-            "forward_snoops": true, 
-            "writeback_clean": false, 
-            "hit_latency": 20, 
-            "tgts_per_mshr": 12, 
-            "demand_mshr_reserve": 1, 
-            "addr_ranges": [
-                "0:18446744073709551615"
-            ], 
-            "is_read_only": false, 
-            "prefetch_on_access": false, 
-            "path": "system.l2c", 
-            "name": "l2c", 
-            "mshrs": 20, 
-            "sequential_access": false, 
-            "assoc": 8
-        }, 
-        "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", 
-        "intel_mp_table": {
-            "oem_table_addr": 0, 
-            "name": "intel_mp_table", 
-            "ext_entries": [
-                {
-                    "parent_bus": 0, 
-                    "name": "ext_entries", 
-                    "type": "X86IntelMPBusHierarchy", 
-                    "subtractive_decode": true, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::IntelMP::BusHierarchy", 
-                    "path": "system.intel_mp_table.ext_entries", 
-                    "bus_id": 1
-                }
-            ], 
-            "oem_id": "", 
-            "eventq_index": 0, 
-            "spec_rev": 4, 
-            "base_entries": [
-                {
-                    "enable": true, 
-                    "local_apic_version": 20, 
-                    "name": "base_entries00", 
-                    "family": 0, 
-                    "local_apic_id": 0, 
-                    "bootstrap": true, 
-                    "feature_flags": 0, 
-                    "eventq_index": 0, 
-                    "stepping": 0, 
-                    "cxx_class": "X86ISA::IntelMP::Processor", 
-                    "path": "system.intel_mp_table.base_entries00", 
-                    "model": 0, 
-                    "type": "X86IntelMPProcessor"
-                }, 
-                {
-                    "enable": true, 
-                    "name": "base_entries01", 
-                    "cxx_class": "X86ISA::IntelMP::IOAPIC", 
-                    "version": 17, 
-                    "eventq_index": 0, 
-                    "address": 4273995776, 
-                    "path": "system.intel_mp_table.base_entries01", 
-                    "type": "X86IntelMPIOAPIC", 
-                    "id": 1
-                }, 
-                {
-                    "bus_type": "PCI", 
-                    "name": "base_entries02", 
-                    "type": "X86IntelMPBus", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::IntelMP::Bus", 
-                    "path": "system.intel_mp_table.base_entries02", 
-                    "bus_id": 0
-                }, 
-                {
-                    "bus_type": "ISA", 
-                    "name": "base_entries03", 
-                    "type": "X86IntelMPBus", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::IntelMP::Bus", 
-                    "path": "system.intel_mp_table.base_entries03", 
-                    "bus_id": 1
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries04", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 0, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 16, 
-                    "path": "system.intel_mp_table.base_entries04", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 16
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries05", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries05", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 0
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries06", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 2, 
-                    "path": "system.intel_mp_table.base_entries06", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 0
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries07", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries07", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 1
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries08", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 1, 
-                    "path": "system.intel_mp_table.base_entries08", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 1
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries09", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries09", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 3
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries10", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 3, 
-                    "path": "system.intel_mp_table.base_entries10", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 3
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries11", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries11", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 4
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries12", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 4, 
-                    "path": "system.intel_mp_table.base_entries12", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 4
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries13", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries13", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 5
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries14", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 5, 
-                    "path": "system.intel_mp_table.base_entries14", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 5
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries15", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries15", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 6
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries16", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 6, 
-                    "path": "system.intel_mp_table.base_entries16", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 6
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries17", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries17", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 7
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries18", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 7, 
-                    "path": "system.intel_mp_table.base_entries18", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 7
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries19", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries19", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 8
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries20", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 8, 
-                    "path": "system.intel_mp_table.base_entries20", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 8
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries21", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries21", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 9
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries22", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 9, 
-                    "path": "system.intel_mp_table.base_entries22", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 9
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries23", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
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-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries23", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 10
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries24", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 10, 
-                    "path": "system.intel_mp_table.base_entries24", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 10
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries25", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries25", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 11
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries26", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
-                    "eventq_index": 0, 
-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 11, 
-                    "path": "system.intel_mp_table.base_entries26", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 11
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries27", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
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-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries27", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 12
-                }, 
-                {
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-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries28", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
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-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 12, 
-                    "path": "system.intel_mp_table.base_entries28", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 12
-                }, 
-                {
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-                    "name": "base_entries29", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
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-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 0, 
-                    "path": "system.intel_mp_table.base_entries29", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 13
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries30", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
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-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 13, 
-                    "path": "system.intel_mp_table.base_entries30", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 13
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries31", 
-                    "interrupt_type": "ExtInt", 
-                    "trigger": "ConformTrigger", 
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-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
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-                    "path": "system.intel_mp_table.base_entries31", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 14
-                }, 
-                {
-                    "polarity": "ConformPolarity", 
-                    "dest_io_apic_id": 1, 
-                    "name": "base_entries32", 
-                    "interrupt_type": "INT", 
-                    "trigger": "ConformTrigger", 
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-                    "source_bus_id": 1, 
-                    "cxx_class": "X86ISA::IntelMP::IOIntAssignment", 
-                    "dest_io_apic_intin": 14, 
-                    "path": "system.intel_mp_table.base_entries32", 
-                    "type": "X86IntelMPIOIntAssignment", 
-                    "source_bus_irq": 14
-                }
-            ], 
-            "cxx_class": "X86ISA::IntelMP::ConfigTable", 
-            "path": "system.intel_mp_table", 
-            "type": "X86IntelMPConfigTable", 
-            "local_apic": 4276092928, 
-            "oem_table_size": 0, 
-            "product_id": ""
-        }, 
-        "cxx_class": "LinuxX86System", 
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-        "iocache": {
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-                "role": "SLAVE"
-            }, 
-            "clusivity": "mostly_incl", 
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-            "clk_domain": "system.clk_domain", 
-            "write_buffers": 8, 
-            "response_latency": 50, 
-            "cxx_class": "Cache", 
-            "size": 1024, 
-            "tags": {
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-                "clk_domain": "system.clk_domain", 
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-                "assoc": 8, 
-                "cxx_class": "LRU", 
-                "path": "system.iocache.tags", 
-                "block_size": 64, 
-                "type": "LRU", 
-                "size": 1024
-            }, 
-            "system": "system", 
-            "max_miss_count": 0, 
-            "eventq_index": 0, 
-            "mem_side": {
-                "peer": "system.membus.slave[4]", 
-                "role": "MASTER"
-            }, 
-            "type": "Cache", 
-            "forward_snoops": false, 
-            "writeback_clean": false, 
-            "hit_latency": 50, 
-            "tgts_per_mshr": 12, 
-            "demand_mshr_reserve": 1, 
-            "addr_ranges": [
-                "0:134217727"
-            ], 
-            "is_read_only": false, 
-            "prefetch_on_access": false, 
-            "path": "system.iocache", 
-            "name": "iocache", 
-            "mshrs": 20, 
-            "sequential_access": false, 
-            "assoc": 8
-        }, 
-        "intel_mp_pointer": {
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-            "name": "intel_mp_pointer", 
-            "spec_rev": 4, 
-            "eventq_index": 0, 
-            "cxx_class": "X86ISA::IntelMP::FloatingPointer", 
-            "path": "system.intel_mp_pointer", 
-            "type": "X86IntelMPFloatingPointer", 
-            "default_config": 0
-        }, 
-        "memories": [
-            "system.physmem"
-        ], 
-        "acpi_description_table_pointer": {
-            "name": "acpi_description_table_pointer", 
-            "cxx_class": "X86ISA::ACPI::RSDP", 
-            "xsdt": {
-                "oem_table_id": "", 
-                "name": "xsdt", 
-                "entries": [], 
-                "creator_revision": 0, 
-                "creator_id": "", 
-                "oem_id": "", 
-                "eventq_index": 0, 
-                "cxx_class": "X86ISA::ACPI::XSDT", 
-                "path": "system.acpi_description_table_pointer.xsdt", 
-                "oem_revision": 0, 
-                "type": "X86ACPIXSDT"
-            }, 
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-            "eventq_index": 0, 
-            "oem_id": "", 
-            "path": "system.acpi_description_table_pointer", 
-            "type": "X86ACPIRSDP", 
-            "revision": 2
-        }, 
-        "clk_domain": {
-            "name": "clk_domain", 
-            "clock": [
-                1000
-            ], 
-            "init_perf_level": 0, 
-            "voltage_domain": "system.voltage_domain", 
-            "eventq_index": 0, 
-            "cxx_class": "SrcClockDomain", 
-            "path": "system.clk_domain", 
-            "type": "SrcClockDomain", 
-            "domain_id": -1
-        }, 
-        "mem_ranges": [
-            "0:134217727"
-        ], 
-        "membus": {
-            "default": {
-                "peer": "system.membus.badaddr_responder.pio", 
-                "role": "MASTER"
-            }, 
-            "slave": {
-                "peer": [
-                    "system.apicbridge.master", 
-                    "system.system_port", 
-                    "system.l2c.mem_side", 
-                    "system.cpu0.interrupts.int_master", 
-                    "system.iocache.mem_side"
-                ], 
-                "role": "SLAVE"
-            }, 
-            "name": "membus", 
-            "badaddr_responder": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "badaddr_responder", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.membus.default", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": true, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.membus.badaddr_responder", 
-                "pio_addr": 0, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "snoop_filter": null, 
-            "forward_latency": 4, 
-            "clk_domain": "system.clk_domain", 
-            "system": "system", 
-            "width": 16, 
-            "eventq_index": 0, 
-            "master": {
-                "peer": [
-                    "system.bridge.slave", 
-                    "system.cpu0.interrupts.pio", 
-                    "system.cpu0.interrupts.int_slave", 
-                    "system.physmem.port"
-                ], 
-                "role": "MASTER"
-            }, 
-            "response_latency": 2, 
-            "cxx_class": "CoherentXBar", 
-            "path": "system.membus", 
-            "snoop_response_latency": 4, 
-            "type": "CoherentXBar", 
-            "use_default_range": false, 
-            "frontend_latency": 3
-        }, 
-        "pc": {
-            "fake_com_4": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_com_4", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[16]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.fake_com_4", 
-                "pio_addr": 9223372036854776552, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "fake_com_2": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_com_2", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[14]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.fake_com_2", 
-                "pio_addr": 9223372036854776568, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "name": "pc", 
-            "south_bridge": {
-                "int_lines": [
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-                        "name": "int_lines0", 
-                        "source": "system.pc.south_bridge.pic1.output", 
-                        "eventq_index": 0, 
-                        "sink": {
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-                            "number": 0, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.io_apic", 
-                            "path": "system.pc.south_bridge.int_lines0.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines0", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
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-                        "source": "system.pc.south_bridge.pic2.output", 
-                        "eventq_index": 0, 
-                        "sink": {
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-                            "number": 2, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.pic1", 
-                            "path": "system.pc.south_bridge.int_lines1.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines1", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
-                        "name": "int_lines2", 
-                        "source": "system.pc.south_bridge.cmos.int_pin", 
-                        "eventq_index": 0, 
-                        "sink": {
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-                            "number": 0, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.pic2", 
-                            "path": "system.pc.south_bridge.int_lines2.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines2", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
-                        "name": "int_lines3", 
-                        "source": "system.pc.south_bridge.pit.int_pin", 
-                        "eventq_index": 0, 
-                        "sink": {
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-                            "number": 0, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.pic1", 
-                            "path": "system.pc.south_bridge.int_lines3.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines3", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
-                        "name": "int_lines4", 
-                        "source": "system.pc.south_bridge.pit.int_pin", 
-                        "eventq_index": 0, 
-                        "sink": {
-                            "name": "sink", 
-                            "number": 2, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.io_apic", 
-                            "path": "system.pc.south_bridge.int_lines4.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines4", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
-                        "name": "int_lines5", 
-                        "source": "system.pc.south_bridge.keyboard.keyboard_int_pin", 
-                        "eventq_index": 0, 
-                        "sink": {
-                            "name": "sink", 
-                            "number": 1, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.io_apic", 
-                            "path": "system.pc.south_bridge.int_lines5.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines5", 
-                        "type": "X86IntLine"
-                    }, 
-                    {
-                        "name": "int_lines6", 
-                        "source": "system.pc.south_bridge.keyboard.mouse_int_pin", 
-                        "eventq_index": 0, 
-                        "sink": {
-                            "name": "sink", 
-                            "number": 12, 
-                            "eventq_index": 0, 
-                            "cxx_class": "X86ISA::IntSinkPin", 
-                            "device": "system.pc.south_bridge.io_apic", 
-                            "path": "system.pc.south_bridge.int_lines6.sink", 
-                            "type": "X86IntSinkPin"
-                        }, 
-                        "cxx_class": "X86ISA::IntLine", 
-                        "path": "system.pc.south_bridge.int_lines6", 
-                        "type": "X86IntLine"
-                    }
-                ], 
-                "name": "south_bridge", 
-                "speaker": {
-                    "name": "speaker", 
-                    "pio": {
-                        "peer": "system.iobus.master[8]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::Speaker", 
-                    "path": "system.pc.south_bridge.speaker", 
-                    "pio_addr": 9223372036854775905, 
-                    "type": "PcSpeaker", 
-                    "i8254": "system.pc.south_bridge.pit"
-                }, 
-                "keyboard": {
-                    "system": "system", 
-                    "command_port": 9223372036854775908, 
-                    "name": "keyboard", 
-                    "pio": {
-                        "peer": "system.iobus.master[4]", 
-                        "role": "SLAVE"
-                    }, 
-                    "mouse_int_pin": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.keyboard.mouse_int_pin", 
-                        "type": "X86IntSourcePin", 
-                        "name": "mouse_int_pin", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "keyboard_int_pin": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.keyboard.keyboard_int_pin", 
-                        "type": "X86IntSourcePin", 
-                        "name": "keyboard_int_pin", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::I8042", 
-                    "path": "system.pc.south_bridge.keyboard", 
-                    "pio_addr": 0, 
-                    "data_port": 9223372036854775904, 
-                    "type": "I8042"
-                }, 
-                "pit": {
-                    "name": "pit", 
-                    "pio": {
-                        "peer": "system.iobus.master[7]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "int_pin": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.pit.int_pin", 
-                        "type": "X86IntSourcePin", 
-                        "name": "int_pin", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::I8254", 
-                    "path": "system.pc.south_bridge.pit", 
-                    "pio_addr": 9223372036854775872, 
-                    "type": "I8254"
-                }, 
-                "io_apic": {
-                    "int_master": {
-                        "peer": "system.iobus.slave[2]", 
-                        "role": "MASTER"
-                    }, 
-                    "name": "io_apic", 
-                    "pio": {
-                        "peer": "system.iobus.master[9]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "external_int_pic": "system.pc.south_bridge.pic1", 
-                    "system": "system", 
-                    "apic_id": 1, 
-                    "int_latency": 1000, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::I82094AA", 
-                    "path": "system.pc.south_bridge.io_apic", 
-                    "pio_addr": 4273995776, 
-                    "type": "I82094AA"
-                }, 
-                "pic1": {
-                    "slave": "system.pc.south_bridge.pic2", 
-                    "name": "pic1", 
-                    "output": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.pic1.output", 
-                        "type": "X86IntSourcePin", 
-                        "name": "output", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "pio": {
-                        "peer": "system.iobus.master[5]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "mode": "I8259Master", 
-                    "cxx_class": "X86ISA::I8259", 
-                    "path": "system.pc.south_bridge.pic1", 
-                    "pio_addr": 9223372036854775840, 
-                    "type": "I8259"
-                }, 
-                "pic2": {
-                    "slave": null, 
-                    "name": "pic2", 
-                    "output": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.pic2.output", 
-                        "type": "X86IntSourcePin", 
-                        "name": "output", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "pio": {
-                        "peer": "system.iobus.master[6]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "mode": "I8259Slave", 
-                    "cxx_class": "X86ISA::I8259", 
-                    "path": "system.pc.south_bridge.pic2", 
-                    "pio_addr": 9223372036854775968, 
-                    "type": "I8259"
-                }, 
-                "platform": "system.pc", 
-                "dma1": {
-                    "name": "dma1", 
-                    "pio": {
-                        "peer": "system.iobus.master[2]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::I8237", 
-                    "path": "system.pc.south_bridge.dma1", 
-                    "pio_addr": 9223372036854775808, 
-                    "type": "I8237"
-                }, 
-                "eventq_index": 0, 
-                "cxx_class": "SouthBridge", 
-                "path": "system.pc.south_bridge", 
-                "ide": {
-                    "PMCAPNextCapability": 0, 
-                    "InterruptPin": 1, 
-                    "HeaderType": 0, 
-                    "VendorID": 32902, 
-                    "MSIXMsgCtrl": 0, 
-                    "MSIXCAPNextCapability": 0, 
-                    "PXCAPLinkCtrl": 0, 
-                    "Revision": 0, 
-                    "LegacyIOBase": 9223372036854775808, 
-                    "pio_latency": 30000, 
-                    "PXCAPLinkCap": 0, 
-                    "CapabilityPtr": 0, 
-                    "MSIXCAPBaseOffset": 0, 
-                    "PXCAPDevCapabilities": 0, 
-                    "MSIXCAPCapId": 0, 
-                    "BAR3Size": 3, 
-                    "PXCAPCapabilities": 0, 
-                    "SubsystemID": 0, 
-                    "PXCAPCapId": 0, 
-                    "BAR4": 1, 
-                    "BAR1": 1012, 
-                    "BAR0": 496, 
-                    "BAR3": 884, 
-                    "BAR2": 368, 
-                    "BAR5": 1, 
-                    "PXCAPDevStatus": 0, 
-                    "disks": [
-                        {
-                            "driveID": "master", 
-                            "name": "disks0", 
-                            "image": {
-                                "read_only": false, 
-                                "name": "image", 
-                                "cxx_class": "CowDiskImage", 
-                                "eventq_index": 0, 
-                                "child": {
-                                    "read_only": true, 
-                                    "name": "child", 
-                                    "eventq_index": 0, 
-                                    "cxx_class": "RawDiskImage", 
-                                    "path": "system.pc.south_bridge.ide.disks0.image.child", 
-                                    "image_file": "/work/gem5/dist/disks/linux-x86.img", 
-                                    "type": "RawDiskImage"
-                                }, 
-                                "path": "system.pc.south_bridge.ide.disks0.image", 
-                                "image_file": "", 
-                                "type": "CowDiskImage", 
-                                "table_size": 65536
-                            }, 
-                            "delay": 1000000, 
-                            "eventq_index": 0, 
-                            "cxx_class": "IdeDisk", 
-                            "path": "system.pc.south_bridge.ide.disks0", 
-                            "type": "IdeDisk"
-                        }, 
-                        {
-                            "driveID": "master", 
-                            "name": "disks1", 
-                            "image": {
-                                "read_only": false, 
-                                "name": "image", 
-                                "cxx_class": "CowDiskImage", 
-                                "eventq_index": 0, 
-                                "child": {
-                                    "read_only": true, 
-                                    "name": "child", 
-                                    "eventq_index": 0, 
-                                    "cxx_class": "RawDiskImage", 
-                                    "path": "system.pc.south_bridge.ide.disks1.image.child", 
-                                    "image_file": "/work/gem5/dist/disks/linux-bigswap2.img", 
-                                    "type": "RawDiskImage"
-                                }, 
-                                "path": "system.pc.south_bridge.ide.disks1.image", 
-                                "image_file": "", 
-                                "type": "CowDiskImage", 
-                                "table_size": 65536
-                            }, 
-                            "delay": 1000000, 
-                            "eventq_index": 0, 
-                            "cxx_class": "IdeDisk", 
-                            "path": "system.pc.south_bridge.ide.disks1", 
-                            "type": "IdeDisk"
-                        }
-                    ], 
-                    "BAR2Size": 8, 
-                    "MSICAPNextCapability": 0, 
-                    "ExpansionROM": 0, 
-                    "MSICAPMsgCtrl": 0, 
-                    "BAR5Size": 0, 
-                    "CardbusCIS": 0, 
-                    "MSIXPbaOffset": 0, 
-                    "MSICAPBaseOffset": 0, 
-                    "MaximumLatency": 0, 
-                    "BAR2LegacyIO": true, 
-                    "LatencyTimer": 0, 
-                    "BAR4LegacyIO": false, 
-                    "PXCAPLinkStatus": 0, 
-                    "PXCAPDevCap2": 0, 
-                    "PXCAPDevCtrl": 0, 
-                    "MSICAPMaskBits": 0, 
-                    "host": "system.pc.pci_host", 
-                    "Command": 0, 
-                    "SubClassCode": 1, 
-                    "pci_func": 0, 
-                    "BAR5LegacyIO": false, 
-                    "MSICAPMsgData": 0, 
-                    "BIST": 0, 
-                    "PXCAPDevCtrl2": 0, 
-                    "pci_bus": 0, 
-                    "InterruptLine": 14, 
-                    "MSICAPMsgAddr": 0, 
-                    "BAR3LegacyIO": true, 
-                    "BAR4Size": 16, 
-                    "path": "system.pc.south_bridge.ide", 
-                    "MinimumGrant": 0, 
-                    "Status": 640, 
-                    "BAR0Size": 8, 
-                    "system": "system", 
-                    "name": "ide", 
-                    "PXCAPNextCapability": 0, 
-                    "eventq_index": 0, 
-                    "type": "IdeController", 
-                    "ctrl_offset": 0, 
-                    "PXCAPBaseOffset": 0, 
-                    "DeviceID": 28945, 
-                    "io_shift": 0, 
-                    "CacheLineSize": 0, 
-                    "dma": {
-                        "peer": "system.iobus.slave[1]", 
-                        "role": "MASTER"
-                    }, 
-                    "PMCAPCapId": 0, 
-                    "config_latency": 20000, 
-                    "BAR1Size": 3, 
-                    "pio": {
-                        "peer": "system.iobus.master[3]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pci_dev": 4, 
-                    "PMCAPCtrlStatus": 0, 
-                    "cxx_class": "IdeController", 
-                    "clk_domain": "system.clk_domain", 
-                    "SubsystemVendorID": 0, 
-                    "PMCAPBaseOffset": 0, 
-                    "MSICAPPendingBits": 0, 
-                    "MSIXTableOffset": 0, 
-                    "MSICAPMsgUpperAddr": 0, 
-                    "MSICAPCapId": 0, 
-                    "BAR0LegacyIO": true, 
-                    "ProgIF": 128, 
-                    "BAR1LegacyIO": true, 
-                    "PMCAPCapabilities": 0, 
-                    "ClassCode": 1
-                }, 
-                "type": "SouthBridge", 
-                "cmos": {
-                    "name": "cmos", 
-                    "pio": {
-                        "peer": "system.iobus.master[1]", 
-                        "role": "SLAVE"
-                    }, 
-                    "pio_latency": 100000, 
-                    "time": "Sun Jan  1 00:00:00 2012", 
-                    "int_pin": {
-                        "eventq_index": 0, 
-                        "path": "system.pc.south_bridge.cmos.int_pin", 
-                        "type": "X86IntSourcePin", 
-                        "name": "int_pin", 
-                        "cxx_class": "X86ISA::IntSourcePin"
-                    }, 
-                    "clk_domain": "system.clk_domain", 
-                    "system": "system", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::Cmos", 
-                    "path": "system.pc.south_bridge.cmos", 
-                    "pio_addr": 9223372036854775920, 
-                    "type": "Cmos"
-                }
-            }, 
-            "fake_floppy": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_floppy", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[17]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 2, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.fake_floppy", 
-                "pio_addr": 9223372036854776818, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "i_dont_exist2": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "i_dont_exist2", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[11]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 1, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.i_dont_exist2", 
-                "pio_addr": 9223372036854776045, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "system": "system", 
-            "i_dont_exist1": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "i_dont_exist1", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[10]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
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-                "pio_size": 1, 
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-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.i_dont_exist1", 
-                "pio_addr": 9223372036854775936, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "intrctrl": "system.intrctrl", 
-            "com_1": {
-                "name": "com_1", 
-                "pio": {
-                    "peer": "system.iobus.master[13]", 
-                    "role": "SLAVE"
-                }, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "terminal": {
-                    "name": "terminal", 
-                    "output": true, 
-                    "number": 0, 
-                    "intr_control": "system.intrctrl", 
-                    "eventq_index": 0, 
-                    "cxx_class": "Terminal", 
-                    "path": "system.pc.com_1.terminal", 
-                    "type": "Terminal", 
-                    "port": 3456
-                }, 
-                "platform": "system.pc", 
-                "eventq_index": 0, 
-                "cxx_class": "Uart8250", 
-                "path": "system.pc.com_1", 
-                "pio_addr": 9223372036854776824, 
-                "type": "Uart8250"
-            }, 
-            "pci_host": {
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-                "name": "pci_host", 
-                "conf_device_bits": 8, 
-                "pio": {
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-                    "role": "SLAVE"
-                }, 
-                "conf_base": 13835058055282163712, 
-                "clk_domain": "system.clk_domain", 
-                "system": "system", 
-                "pci_dma_base": 0, 
-                "platform": "system.pc", 
-                "eventq_index": 0, 
-                "cxx_class": "GenericPciHost", 
-                "path": "system.pc.pci_host", 
-                "pci_pio_base": 9223372036854775808, 
-                "type": "GenericPciHost", 
-                "pci_mem_base": 0
-            }, 
-            "eventq_index": 0, 
-            "cxx_class": "Pc", 
-            "path": "system.pc", 
-            "behind_pci": {
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-                "ret_data8": 255, 
-                "name": "behind_pci", 
-                "warn_access": "", 
-                "pio": {
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-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
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-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.behind_pci", 
-                "pio_addr": 9223372036854779128, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }, 
-            "type": "Pc", 
-            "fake_com_3": {
-                "system": "system", 
-                "ret_data8": 255, 
-                "name": "fake_com_3", 
-                "warn_access": "", 
-                "pio": {
-                    "peer": "system.iobus.master[15]", 
-                    "role": "SLAVE"
-                }, 
-                "ret_bad_addr": false, 
-                "pio_latency": 100000, 
-                "clk_domain": "system.clk_domain", 
-                "fake_mem": false, 
-                "pio_size": 8, 
-                "ret_data32": 4294967295, 
-                "eventq_index": 0, 
-                "update_data": false, 
-                "ret_data64": 18446744073709551615, 
-                "cxx_class": "IsaFake", 
-                "path": "system.pc.fake_com_3", 
-                "pio_addr": 9223372036854776808, 
-                "type": "IsaFake", 
-                "ret_data16": 65535
-            }
-        }, 
-        "eventq_index": 0, 
-        "e820_table": {
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-            "cxx_class": "X86ISA::E820Table", 
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-            "entries": [
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-                    "range_type": 1, 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::E820Entry", 
-                    "path": "system.e820_table.entries0", 
-                    "size": 654336, 
-                    "type": "X86E820Entry", 
-                    "name": "entries0"
-                }, 
-                {
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-                    "localCtrBits": 2, 
-                    "eventq_index": 0, 
-                    "BTBTagSize": 16, 
-                    "BTBEntries": 4096, 
-                    "cxx_class": "TournamentBP", 
-                    "path": "system.cpu2.branchPred", 
-                    "localPredictorSize": 2048, 
-                    "type": "TournamentBP", 
-                    "RASSize": 16, 
-                    "globalPredictorSize": 8192
-                }, 
-                "LFSTSize": 1024, 
-                "isa": [
-                    {
-                        "eventq_index": 0, 
-                        "path": "system.cpu2.isa", 
-                        "type": "X86ISA", 
-                        "name": "isa", 
-                        "cxx_class": "X86ISA::ISA"
-                    }
-                ], 
-                "smtROBPolicy": "Partitioned", 
-                "iewToFetchDelay": 1, 
-                "do_statistics_insts": true, 
-                "dispatchWidth": 8, 
-                "commitToDecodeDelay": 1, 
-                "smtIQPolicy": "Partitioned", 
-                "issueWidth": 8, 
-                "LSQCheckLoads": true, 
-                "commitToRenameDelay": 1, 
-                "cachePorts": 200, 
-                "system": "system", 
-                "checker": null, 
-                "numPhysFloatRegs": 256, 
-                "eventq_index": 0, 
-                "type": "DerivO3CPU", 
-                "wbWidth": 8, 
-                "interrupts": [], 
-                "smtCommitPolicy": "RoundRobin", 
-                "issueToExecuteDelay": 1, 
-                "dtb": {
-                    "name": "dtb", 
-                    "eventq_index": 0, 
-                    "cxx_class": "X86ISA::TLB", 
-                    "walker": {
-                        "name": "walker", 
-                        "clk_domain": "system.cpu_clk_domain", 
-                        "system": "system", 
-                        "eventq_index": 0, 
-                        "cxx_class": "X86ISA::Walker", 
-                        "path": "system.cpu2.dtb.walker", 
-                        "type": "X86PagetableWalker", 
-                        "num_squash_per_cycle": 4
-                    }, 
-                    "path": "system.cpu2.dtb", 
-                    "type": "X86TLB", 
-                    "size": 64
-                }, 
-                "numROBEntries": 192, 
-                "fetchQueueSize": 32, 
-                "iewToCommitDelay": 1, 
-                "smtNumFetchingThreads": 1, 
-                "forwardComSize": 5, 
-                "do_checkpoint_insts": true, 
-                "cxx_class": "DerivO3CPU", 
-                "commitToIEWDelay": 1, 
-                "commitWidth": 8, 
-                "clk_domain": "system.cpu_clk_domain", 
-                "function_trace_start": 0, 
-                "smtFetchPolicy": "SingleThread", 
-                "profile": 0, 
-                "LSQDepCheckShift": 4, 
-                "trapLatency": 13, 
-                "iewToDecodeDelay": 1, 
-                "numPhysCCRegs": 1280, 
-                "renameToIEWDelay": 2, 
-                "progress_interval": 0, 
-                "LQEntries": 32
-            }
-        ], 
-        "intrctrl": {
-            "name": "intrctrl", 
-            "sys": "system", 
-            "eventq_index": 0, 
-            "cxx_class": "IntrControl", 
-            "path": "system.intrctrl", 
-            "type": "IntrControl"
-        }, 
-        "multi_thread": false, 
-        "work_begin_ckpt_count": 0, 
-        "work_begin_cpu_id_exit": -1, 
-        "work_item_id": -1, 
-        "num_work_ids": 16
-    }, 
-    "time_sync_period": 100000000000, 
-    "eventq_index": 0, 
-    "time_sync_spin_threshold": 100000000, 
-    "cxx_class": "Root", 
-    "path": "root", 
-    "time_sync_enable": false, 
-    "type": "Root", 
-    "full_system": true
-}
\ No newline at end of file
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
deleted file mode 100755 (executable)
index 30a665f..0000000
+++ /dev/null
@@ -1,87 +0,0 @@
-warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: Reading current count from inactive timer.
-warn: Don't know what interrupt to clear for console.
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: x86 cpuid: unknown family 0x8086
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9400, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6996, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12287, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7603, Bank: 3
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10369, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9709, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7701, Bank: 2
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11369, Bank: 1
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: Tried to clear PCI interrupt 14
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8909, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6789, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8215, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8557, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11226, Bank: 4
-warn: Unknown mouse command 0xe1.
-warn: instruction 'wbinvd' unimplemented
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7944, Bank: 0
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
deleted file mode 100755 (executable)
index 73370e2..0000000
+++ /dev/null
@@ -1,10 +0,0 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Dec  4 2015 15:10:31
-gem5 started Dec  4 2015 16:03:32
-gem5 executing on e104799-lin, pid 2775
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
-
-Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
deleted file mode 100644 (file)
index 70169df..0000000
+++ /dev/null
@@ -1,1925 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  5.142303                       # Number of seconds simulated
-sim_ticks                                5142302696000                       # Number of ticks simulated
-final_tick                               5142302696000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 292534                       # Simulator instruction rate (inst/s)
-host_op_rate                                   581577                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6171937350                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 967756                       # Number of bytes of host memory used
-host_seconds                                   833.17                       # Real time elapsed on the host
-sim_insts                                   243732330                       # Number of instructions simulated
-sim_ops                                     484555405                       # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage                       1                       # Voltage in Volts
-system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           495360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5776768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           125248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2074112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         3968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           322688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2420672                       # Number of bytes read from this memory
-system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             11247552                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       495360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       125248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       322688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          943296                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9049984                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9049984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7740                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             90262                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             32408                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           62                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              5042                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             37823                       # Number of read requests responded to by this memory
-system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                175743                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          141406                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               141406                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               96330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1123382                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               24356                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              403343                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker            12                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               62752                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              470737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide         5513                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2187260                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          96330                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          24356                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          62752                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             183438                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1759909                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1759909                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1759909                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              96330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1123382                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              24356                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             403343                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          772                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker           12                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              62752                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             470737                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide         5513                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3947169                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         77737                       # Number of read requests accepted
-system.physmem.writeReqs                        69857                       # Number of write requests accepted
-system.physmem.readBursts                       77737                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      69857                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  4969408                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5760                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4469312                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   4975168                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4470848                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       90                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                4738                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                4587                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5683                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                5272                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                4460                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                4242                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                4391                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                4725                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                4783                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                4859                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               4723                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               4859                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               4897                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               5764                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               5025                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               4639                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4788                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4346                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4813                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4456                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4399                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4368                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4481                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4596                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3541                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                3660                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               3623                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4308                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4463                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               5017                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4599                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4375                       # Per bank write bursts
-system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5141302561000                       # Total gap between requests
-system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   77737                       # Read request sizes (log2)
-system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  69857                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     73816                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      3057                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       363                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       113                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        36                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        34                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                       24                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        2                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                        70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                        64                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                        60                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                        59                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                        55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3481                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3524                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3947                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4206                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     3967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     3931                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     3499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     3423                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     3455                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      115                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       95                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       84                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       87                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       94                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       88                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       78                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       91                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       73                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       56                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       68                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56                       34                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        34726                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      271.798192                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     162.605386                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     302.611478                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          14316     41.23%     41.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8644     24.89%     66.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         3494     10.06%     76.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1847      5.32%     81.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1254      3.61%     85.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          948      2.73%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          605      1.74%     89.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          474      1.36%     90.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3144      9.05%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          34726                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          3354                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.146989                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      204.184053                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            3351     99.91%     99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535            1      0.03%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::5632-6143            1      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9728-10239            1      0.03%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            3354                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          3354                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        20.820811                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       18.786469                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev       13.927460                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3                11      0.33%      0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7                 7      0.21%      0.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15               8      0.24%      0.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19            2796     83.36%     84.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23              40      1.19%     85.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              43      1.28%     86.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31              85      2.53%     89.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35             115      3.43%     92.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39              62      1.85%     94.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43              12      0.36%     94.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               6      0.18%     94.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51              11      0.33%     95.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               4      0.12%     95.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               2      0.06%     95.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.06%     95.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67             122      3.64%     99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               2      0.06%     99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75               1      0.03%     99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79               2      0.06%     99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83               3      0.09%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87               1      0.03%     99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95               1      0.03%     99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.03%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115             1      0.03%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.03%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131             8      0.24%     99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135             1      0.03%     99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143             1      0.03%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.03%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163             1      0.03%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167             1      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195             2      0.06%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            3354                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      822128507                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2278009757                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    388235000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10588.03                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29338.03                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           0.97                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.87                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        0.97                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.87                       # Average system write bandwidth in MiByte/s
-system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         3.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      61504                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51248                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.21                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.36                       # Row buffer hit rate for writes
-system.physmem.avgGap                     34834089.20                       # Average gap between requests
-system.physmem.pageHitRate                      76.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  129729600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   70607625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 297164400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                234880560                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy           250511061840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            94606706745                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           2237443433250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             2583293584020                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              667.968853                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   3690534116962                       # Time in different power states
-system.physmem_0.memoryStateTime::REF    128073140000                       # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     17232140788                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  132798960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   72319500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 308451000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                217637280                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy           250511061840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            94562869185                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           2235084583500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             2580889721265                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.037449                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   3690605945988                       # Time in different power states
-system.physmem_1.memoryStateTime::REF    128073140000                       # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17153124512                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                       902046715                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.committedInsts                   73959427                       # Number of instructions committed
-system.cpu0.committedOps                    150307597                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            138246700                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1066960                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14495182                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   138246700                       # number of integer instructions
-system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          254560897                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         118518911                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            85690938                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           57098279                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     14889374                       # number of memory refs
-system.cpu0.num_load_insts                   10848208                       # Number of load instructions
-system.cpu0.num_store_insts                   4041166                       # Number of store instructions
-system.cpu0.num_idle_cycles              853760386.040518                       # Number of idle cycles
-system.cpu0.num_busy_cycles              48286328.959482                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.053530                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.946470                       # Percentage of idle cycles
-system.cpu0.Branches                         15948833                       # Number of branches fetched
-system.cpu0.op_class::No_OpClass                97349      0.06%      0.06% # Class of executed instruction
-system.cpu0.op_class::IntAlu                135200596     89.95%     90.01% # Class of executed instruction
-system.cpu0.op_class::IntMult                   70034      0.05%     90.06% # Class of executed instruction
-system.cpu0.op_class::IntDiv                    52579      0.03%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatAdd                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatCmp                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatCvt                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatMult                     0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatDiv                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt                     0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAdd                       0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc                    0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdAlu                       0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdCmp                       0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdCvt                       0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMisc                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMult                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc                   0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdShift                     0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt                      0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv                  0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc                 0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult                 0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     90.10% # Class of executed instruction
-system.cpu0.op_class::MemRead                10846498      7.22%     97.31% # Class of executed instruction
-system.cpu0.op_class::MemWrite                4041166      2.69%    100.00% # Class of executed instruction
-system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu0.op_class::total                 150308222                       # Class of executed instruction
-system.cpu0.dcache.tags.replacements          1651251                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.996861                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           20452818                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1651763                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            12.382417                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   417.977148                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data    68.931894                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data    25.087819                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.816362                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.134633                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.049000                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         91512129                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        91512129                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5600779                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2451508                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4254630                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       12306917                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3889675                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1677991                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2514442                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8082108                       # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data        23860                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data        10736                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data        27491                       # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total        62087                       # number of SoftPFReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9490454                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4129499                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6769072                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        20389025                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9514314                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4140235                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6796563                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       20451112                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       387262                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       176472                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       719884                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1283618                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       146675                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        64233                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       112265                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       323173                       # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data       158823                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data        68896                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data       179464                       # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total       407183                       # number of SoftPFReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       533937                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       240705                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       832149                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1606791                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       692760                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       309601                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1011613                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2013974                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2460813500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9669943500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  12130757000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2732722991                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3586634440                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   6319357431                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5193536491                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  13256577940                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  18450114431                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5193536491                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  13256577940                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  18450114431                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5988041                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2627980                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4974514                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13590535                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4036350                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1742224                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2626707                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8405281                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       182683                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        79632                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       206955                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total       469270                       # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     10024391                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4370204                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7601221                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21995816                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     10207074                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4449836                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7808176                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     22465086                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.064673                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.067151                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.144714                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.094449                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.036339                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036868                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.042740                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.038449                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.869391                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.865180                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.867164                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total     0.867695                       # miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.053264                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.055079                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.109476                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.073050                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.067871                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069576                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.129558                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.089649                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13944.498277                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 13432.641231                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  9450.441642                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42543.910311                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31947.930700                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19554.100841                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21576.354837                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 15930.534003                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 11482.585122                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16774.934483                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 13104.396582                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total  9161.048966                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       149019                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            19247                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     7.742453                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.dcache.writebacks::writebacks      1557863                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1557863                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           49                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       325442                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       325491                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data         1624                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        29845                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        31469                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data         1673                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       355287                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       356960                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data         1673                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       355287                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       356960                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       176423                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       394442                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       570865                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        62609                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        82420                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       145029                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        68896                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data       176057                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total       244953                       # number of SoftPFReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       239032                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       476862                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       715894                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       307928                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       652919                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       960847                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data       175968                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data       193387                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total       369355                       # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         2768                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         4032                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total         6800                       # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data       178736                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data       197419                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total       376155                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2283564500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   5222076000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   7505640500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2580696991                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2983674940                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5564371931                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data   1020231000                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data   2452891500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total   3473122500                       # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4864261491                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   8205750940                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  13070012431                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   5884492491                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  10658642440                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16543134931                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30715210000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33235671500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63950881500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30715210000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  33235671500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  63950881500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.067133                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.079293                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.042005                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.035936                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031378                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017255                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.865180                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.850702                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.521987                       # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.054696                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.062735                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032547                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069200                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.083620                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.042771                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12943.689315                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13239.147961                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.837930                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41219.265457                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36200.860713                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38367.305373                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14808.276242                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13932.371334                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14178.730205                       # average SoftPFReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20349.833876                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17207.810520                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18256.910145                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19109.962365                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16324.601428                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17217.241591                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174549.974995                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 171860.939463                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173142.048977                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171846.801987                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 168350.926203                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170012.046896                       # average overall mshr uncacheable latency
-system.cpu0.icache.tags.replacements           956706                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.794700                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          133067935                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           957218                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           139.015287                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     150766905000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   303.387688                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    65.665696                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   141.741316                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.592554                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.128253                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.276839                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997646                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          235                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          169                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        135039924                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       135039924                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     90259731                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     39032907                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3775297                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      133067935                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     90259731                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     39032907                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3775297                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       133067935                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     90259731                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     39032907                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3775297                       # number of overall hits
-system.cpu0.icache.overall_hits::total      133067935                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       368418                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       164616                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       481723                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1014757                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       368418                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       164616                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       481723                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1014757                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       368418                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       164616                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       481723                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1014757                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2280778000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   6376139484                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   8656917484                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2280778000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   6376139484                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   8656917484                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2280778000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   6376139484                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   8656917484                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     90628149                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     39197523                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      4257020                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    134082692                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     90628149                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     39197523                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      4257020                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    134082692                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     90628149                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     39197523                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      4257020                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    134082692                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.004065                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.004200                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.113160                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.007568                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.004065                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.004200                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.113160                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.007568                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.004065                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.004200                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.113160                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.007568                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13855.141663                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13236.111799                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8531.025146                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13855.141663                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13236.111799                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8531.025146                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13855.141663                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13236.111799                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8531.025146                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3656                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              267                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    13.692884                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks       956706                       # number of writebacks
-system.cpu0.icache.writebacks::total           956706                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        57525                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        57525                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        57525                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        57525                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        57525                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        57525                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       164616                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       424198                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       588814                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       164616                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       424198                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       588814                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       164616                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       424198                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       588814                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   2116162000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   5491871486                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   7608033486                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   2116162000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   5491871486                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   7608033486                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   2116162000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   5491871486                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   7608033486                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004391                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004391                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.004200                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.099647                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004391                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12920.945300                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12920.945300                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12855.141663                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12946.481327                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12920.945300                       # average overall mshr miss latency
-system.cpu1.numCycles                      2608017339                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.committedInsts                   35627427                       # Number of instructions committed
-system.cpu1.committedOps                     68998423                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             64051827                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     468203                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6587290                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    64051827                       # number of integer instructions
-system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          118624529                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          55196381                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36419223                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           27076219                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4628508                       # number of memory refs
-system.cpu1.num_load_insts                    2883555                       # Number of load instructions
-system.cpu1.num_store_insts                   1744953                       # Number of store instructions
-system.cpu1.num_idle_cycles              2479194289.218051                       # Number of idle cycles
-system.cpu1.num_busy_cycles              128823049.781949                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.049395                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.950605                       # Percentage of idle cycles
-system.cpu1.Branches                          7222524                       # Number of branches fetched
-system.cpu1.op_class::No_OpClass                27694      0.04%      0.04% # Class of executed instruction
-system.cpu1.op_class::IntAlu                 64285165     93.17%     93.21% # Class of executed instruction
-system.cpu1.op_class::IntMult                   28263      0.04%     93.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv                    29212      0.04%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult                     0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt                     0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd                       0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc                    0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu                       0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp                       0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt                       0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc                   0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift                     0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt                      0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv                  0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc                 0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult                 0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     93.29% # Class of executed instruction
-system.cpu1.op_class::MemRead                 2883455      4.18%     97.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite                1744953      2.53%    100.00% # Class of executed instruction
-system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
-system.cpu1.op_class::total                  68998742                       # Class of executed instruction
-system.cpu2.branchPred.lookups               31199361                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         31199361                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           851763                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            30042490                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                      0                       # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct             0.000000                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 863549                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect            181695                       # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups       30042490                       # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits          24994810                       # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses         5047680                       # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted       585906                       # Number of mispredicted indirect branches.
-system.cpu2.numCycles                       154015967                       # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10525182                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     153136013                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   31199361                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          25858359                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                    140984091                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1735783                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                    143780                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles               16316                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             7923                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        66490                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles           26                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          488                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  4257020                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               368090                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   3025                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples         152611536                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.969429                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.111517                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                95212585     62.39%     62.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  896814      0.59%     62.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23718994     15.54%     78.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  549190      0.36%     78.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  778244      0.51%     79.39% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  799023      0.52%     79.91% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  532989      0.35%     80.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  720428      0.47%     80.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                29403269     19.27%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total           152611536                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.202572                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.994287                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                10167862                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             90185488                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 25340442                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              4831486                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                868543                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             293911699                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                868543                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12378234                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               76415835                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       3891181                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 27683635                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles             10156457                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             290176548                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents               179480                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               5269403                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents                 20140                       # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents               2921556                       # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands          344456385                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            633379614                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       389227303                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups              120                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            317474127                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                26982256                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            189266                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        192828                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 22388341                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             7330700                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            4149427                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           414211                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          341335                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 283979915                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             425629                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                278392066                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued           405323                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined       19156154                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     28402257                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         93435                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples    152611536                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.824188                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.420511                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           90358507     59.21%     59.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            4845557      3.18%     62.38% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            3452107      2.26%     64.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            3415281      2.24%     66.88% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           22680576     14.86%     81.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            2703807      1.77%     83.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           24243891     15.89%     99.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             602713      0.39%     99.80% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8             309097      0.20%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total      152611536                       # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                1789790     87.09%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     87.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                208308     10.14%     97.22% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                57058      2.78%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass           101487      0.04%      0.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            267636712     96.14%     96.17% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               50542      0.02%     96.19% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                41904      0.02%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                 34      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.21% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             7148788      2.57%     98.77% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3412599      1.23%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             278392066                       # Type of FU issued
-system.cpu2.iq.rate                          1.807553                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    2055156                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007382                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         711855943                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        303565687                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    275033680                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                203                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               174                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           83                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             280345636                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     99                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          602114                       # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      2634716                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses        13210                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         5396                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores      1520030                       # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       706535                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        19267                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                868543                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles               71343644                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles              2239546                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          284405544                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            59883                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              7330707                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             4149427                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            256703                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                145075                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents              1788429                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          5396                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        270430                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       847907                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts             1118337                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            276410000                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6693207                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts          1826872                       # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9818298                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                27929809                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3125091                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.794684                       # Inst execution rate
-system.cpu2.iew.wb_sent                     275971770                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    275033763                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                214243041                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                350261962                       # num instructions consuming a value
-system.cpu2.iew.wb_rate                      1.785748                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.611665                       # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts       19130941                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         332194                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           855634                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples    149565660                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.773464                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.653305                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     93221920     62.33%     62.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      3884084      2.60%     64.93% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1108913      0.74%     65.67% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24362236     16.29%     81.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       961331      0.64%     82.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       644406      0.43%     83.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       409687      0.27%     83.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23249373     15.54%     98.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1723710      1.15%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total    149565660                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           134145476                       # Number of instructions committed
-system.cpu2.commit.committedOps             265249385                       # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       7325387                       # Number of memory references committed
-system.cpu2.commit.loads                      4695990                       # Number of loads committed
-system.cpu2.commit.membars                     151817                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27066281                       # Number of branches committed
-system.cpu2.commit.fp_insts                        48                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                241954507                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              387238                       # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass        47651      0.02%      0.02% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu       257791047     97.19%     97.21% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult          45496      0.02%     97.22% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv           40577      0.02%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt            16      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     97.24% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead        4695201      1.77%     99.01% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite       2629397      0.99%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total        265249385                       # Class of committed instruction
-system.cpu2.commit.bw_lim_events              1723710                       # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads                   432186718                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  571865889                       # The number of ROB writes
-system.cpu2.timesIdled                         138407                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        1404431                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4914533165                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  134145476                       # Number of Instructions Simulated
-system.cpu2.committedOps                    265249385                       # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi                              1.148126                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.148126                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.870984                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.870984                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               365815904                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              220629753                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    73051                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                138624705                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               107019387                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               89775262                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                129105                       # number of misc regfile writes
-system.iobus.trans_dist::ReadReq              3544820                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             3544820                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               57702                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              57702                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1686                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1686                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio      7065558                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1126                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27910                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio         2308                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      7109792                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95252                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95252                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3372                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3372                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                 7208416                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      3532779                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2252                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13955                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio         4477                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total      3561050                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6744                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total                  6595586                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy              2583988                       # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy                36000                       # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4499500                       # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer4.occupancy               934500                       # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy                19000                       # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                17500                       # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer8.occupancy            199160500                       # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy               352000                       # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy               77500                       # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            13461500                       # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer16.occupancy               11500                       # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           119181081                       # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer19.occupancy             1081000                       # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           283709000                       # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            25934000                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1055000                       # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47571                       # number of replacements
-system.iocache.tags.tagsinuse                0.093993                       # Cycle average of tags in use
-system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47587                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5004596403009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.093993                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005875                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005875                       # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428634                       # Number of tag accesses
-system.iocache.tags.data_accesses              428634                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          906                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              906                       # number of ReadReq misses
-system.iocache.WriteLineReq_misses::pc.south_bridge.ide        46720                       # number of WriteLineReq misses
-system.iocache.WriteLineReq_misses::total        46720                       # number of WriteLineReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47626                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47626                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47626                       # number of overall misses
-system.iocache.overall_misses::total            47626                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    120463801                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    120463801                       # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide   2718328280                       # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total   2718328280                       # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   2838792081                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   2838792081                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   2838792081                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   2838792081                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          906                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            906                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::pc.south_bridge.ide        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.WriteLineReq_accesses::total        46720                       # number of WriteLineReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47626                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47626                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47626                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47626                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
-system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 132962.252759                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 132962.252759                       # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 58183.396404                       # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 58183.396404                       # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 59605.931235                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 59605.931235                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 59605.931235                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 59605.931235                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs           354                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                   28                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    12.642857                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          711                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide        22880                       # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total        22880                       # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        23591                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        23591                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        23591                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        23591                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     84913801                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     84913801                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide   1572541335                       # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total   1572541335                       # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   1657455136                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1657455136                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   1657455136                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1657455136                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.784768                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.784768                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide     0.489726                       # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total     0.489726                       # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.495339                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.495339                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.495339                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.495339                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119428.693390                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 119428.693390                       # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 68729.953453                       # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68729.953453                       # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 70257.943114                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 70257.943114                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 70257.943114                       # average overall mshr miss latency
-system.l2c.tags.replacements                   102742                       # number of replacements
-system.l2c.tags.tagsinuse                64807.232548                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    4917874                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   166881                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    29.469346                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   50676.768734                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131121                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1597.619840                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5190.937172                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.003338                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      233.485852                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1577.800752                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    27.152241                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.957955                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1336.692253                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4165.683291                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.773266                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.024378                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.079207                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003563                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.024075                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000414                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.020396                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.063563                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.988880                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64139                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          571                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3312                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7441                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52737                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.978683                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 43620877                       # Number of tag accesses
-system.l2c.tags.data_accesses                43620877                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        21700                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        11096                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         4762                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         2301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker       121788                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        15231                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                 176878                       # number of ReadReq hits
-system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
-system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.WritebackDirty_hits::writebacks      1557863                       # number of WritebackDirty hits
-system.l2c.WritebackDirty_hits::total         1557863                       # number of WritebackDirty hits
-system.l2c.WritebackClean_hits::writebacks       955842                       # number of WritebackClean hits
-system.l2c.WritebackClean_hits::total          955842                       # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data             146                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              66                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              62                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 274                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            74219                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            34448                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            53501                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               162168                       # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst        360664                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst        162659                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst        419122                       # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total            942445                       # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data       526913                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data       240478                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data       560799                       # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total          1328190                       # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         21700                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         11098                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              360664                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              601132                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          4762                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          2301                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              162659                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              274926                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker        121788                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         15231                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              419122                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              614300                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2609683                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        21700                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        11098                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             360664                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             601132                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         4762                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         2301                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             162659                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             274926                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker       121788                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        15231                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             419122                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             614300                       # number of overall hits
-system.l2c.overall_hits::total                2609683                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           62                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                   68                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           768                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           293                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           283                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1344                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          71542                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          27814                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          28615                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             127971                       # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst         7741                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst         1957                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst         5043                       # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total           14741                       # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data        19172                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data         4841                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data         9660                       # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total          33673                       # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7741                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             90714                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1957                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             32655                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           62                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              5043                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             38275                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                176453                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7741                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            90714                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1957                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            32655                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           62                       # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             5043                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            38275                       # number of overall misses
-system.l2c.overall_misses::total               176453                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker        83500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      5420500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker        83500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total        5587500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      4987500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      4499000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      9486500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   2114236500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2284326500                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   4398563000                       # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst    159298500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst    429808000                       # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total    589106500                       # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data    409237000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data    815088000                       # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total   1224325000                       # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        83500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    159298500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2523473500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      5420500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker        83500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    429808000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3099414500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6217582000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        83500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    159298500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2523473500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      5420500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker        83500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    429808000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3099414500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6217582000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        21700                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        11100                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         4762                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         2302                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker       121850                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        15232                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total             176946                       # number of ReadReq accesses(hits+misses)
-system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
-system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::writebacks      1557863                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackDirty_accesses::total      1557863                       # number of WritebackDirty accesses(hits+misses)
-system.l2c.WritebackClean_accesses::writebacks       955842                       # number of WritebackClean accesses(hits+misses)
-system.l2c.WritebackClean_accesses::total       955842                       # number of WritebackClean accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          914                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          359                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          345                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1618                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       145761                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        62262                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        82116                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           290139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst       368405                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst       164616                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst       424165                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total        957186                       # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data       546085                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data       245319                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data       570459                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total      1361863                       # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        21700                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        11102                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          368405                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          691846                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         4762                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         2302                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          164616                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          307581                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker       121850                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        15232                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          424165                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          652575                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2786136                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        21700                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        11102                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         368405                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         691846                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         4762                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         2302                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         164616                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         307581                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker       121850                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        15232                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         424165                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         652575                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2786136                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.000384                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.840263                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.816156                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.820290                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.830655                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.490817                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.446725                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.348470                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.441068                       # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.021012                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.011888                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.011889                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total     0.015400                       # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.035108                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.019733                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.016934                       # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total     0.024726                       # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.021012                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.131119                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.011888                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.106167                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.011889                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.058652                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.063333                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000360                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.021012                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.131119                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.000434                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.011888                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.106167                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000509                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000066                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.011889                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.058652                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.063333                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        83500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        83500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 82169.117647                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17022.184300                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15897.526502                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  7058.407738                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76013.392536                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79829.687227                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 34371.560744                       # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81399.335718                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 85228.633750                       # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 39963.808425                       # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 84535.633134                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 84377.639752                       # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 36359.249250                       # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81399.335718                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 77276.787628                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        83500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 85228.633750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 80977.517962                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 35236.476569                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        83500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81399.335718                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 77276.787628                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 87427.419355                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        83500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 85228.633750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 80977.517962                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 35236.476569                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.writebacks::writebacks               94739                       # number of writebacks
-system.l2c.writebacks::total                    94739                       # number of writebacks
-system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            1                       # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           62                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total              64                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          293                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          283                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          576                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        27814                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        28615                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         56429                       # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1957                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         5042                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total         6999                       # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data         4841                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data         9660                       # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total        14501                       # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1957                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        32655                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           62                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         5042                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        38275                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            77993                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1957                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        32655                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           62                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         5042                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        38275                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           77993                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data       175968                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data       193387                       # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total       369355                       # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data         2768                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data         4032                       # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total         6800                       # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data       178736                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data       197419                       # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total       376155                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        73500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        73500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total      4947500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      6159500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      5718500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     11878000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1836096500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1998176500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3834273000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    139728500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    379329000                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total    519057500                       # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    360827000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    746886000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total   1107713000                       # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    139728500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   2196923500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        73500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    379329000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2745062500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5465991000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        73500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    139728500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   2196923500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      4800500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        73500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    379329000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2745062500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5465991000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28515609500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30818304000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59333913500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28515609500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  30818304000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59333913500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.000362                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.816156                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.820290                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.355995                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.446725                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.348470                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.194490                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total     0.007312                       # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.019733                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.016934                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total     0.010648                       # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.106167                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.058652                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.027993                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000434                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011888                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.106167                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000509                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000066                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011887                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.058652                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.027993                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77304.687500                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21022.184300                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20206.713781                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20621.527778                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66013.392536                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69829.687227                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 67948.625707                       # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74161.665952                       # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74535.633134                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77317.391304                       # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76388.731812                       # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67276.787628                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71719.464402                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70083.097201                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71399.335718                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67276.787628                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77427.419355                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        73500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75233.835779                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71719.464402                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70083.097201                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162049.972154                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 159360.784334                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160641.966401                       # average ReadReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159540.380785                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156106.068818                       # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 157737.936489                       # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests        375707                       # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests       160970                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests         1170                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq             5049003                       # Transaction distribution
-system.membus.trans_dist::ReadResp            5098173                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13918                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13918                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       141406                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             8879                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             1627                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             897                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            127688                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           127688                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         49387                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1686                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1686                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          217                       # Transaction distribution
-system.membus.trans_dist::InvalidateReq         46720                       # Transaction distribution
-system.membus.trans_dist::InvalidateResp        23840                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         3372                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3372                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      7109792                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio      3016050                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       456814                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          434                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total     10583090                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       119675                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       119675                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               10706137                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         6744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total         6744                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave      3561050                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio      6032097                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17304384                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total     26897531                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      3027520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total      3027520                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                29931795                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops                              596                       # Total snoops (count)
-system.membus.snoop_fanout::samples           5365465                       # Request fanout histogram
-system.membus.snoop_fanout::mean             0.001972                       # Request fanout histogram
-system.membus.snoop_fanout::stdev            0.044366                       # Request fanout histogram
-system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 5354883     99.80%     99.80% # Request fanout histogram
-system.membus.snoop_fanout::1                   10582      0.20%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
-system.membus.snoop_fanout::total             5365465                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           219694000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           286587500                       # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             2585012                       # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           464604174                       # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy              267500                       # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1530012                       # Layer occupancy (ticks)
-system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1157102500                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy            3622087                       # Layer occupancy (ticks)
-system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.snoop_filter.tot_requests      5251700                       # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests      2642649                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests         1467                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops            797                       # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops          797                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq            5252356                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           7571420                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             13920                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            13920                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty      1604861                       # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean       956706                       # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict           97687                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1618                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1618                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           290139                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          290139                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq        957232                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq      1362205                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          217                       # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq         4436                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      2871137                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side     15084519                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        67785                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       321441                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total              18344882                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    122489920                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    215022523                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       256088                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side      1230880                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total              338999411                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops                          130547                       # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples          9049191                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean            0.003896                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev           0.062298                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0                9013933     99.61%     99.61% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1                  35258      0.39%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2                      0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value              1                       # Request fanout histogram
-system.toL2Bus.snoop_fanout::total            9049191                       # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy         3319937995                       # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           330397                       # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy         883646129                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1813359528                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          21309973                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         140489176                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
deleted file mode 100644 (file)
index 2e4dba0..0000000
+++ /dev/null
@@ -1,141 +0,0 @@
-Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
- BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
- BIOS-e820: 0000000008000000 - 00000000c0000000 (reserved)\r
- BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
-end_pfn_map = 1048576\r
-kernel direct mapping tables up to 100000000 @ 8000-d000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
-  DMA             0 ->     4096\r
-  DMA32        4096 ->  1048576\r
-  Normal    1048576 ->  1048576\r
-early_node_map[2] active PFN ranges\r
-    0:        0 ->      159\r
-    0:      256 ->    32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-I/O APIC #1 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 1\r
-swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000\r
-swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000\r
-Allocating PCI resources starting at c4000000 (gap: c0000000:3fff0000)\r
-Built 1 zonelists.  Total pages: 30610\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.003 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 122176k/131072k available (3742k kernel code, 8472k reserved, 1874k data, 232k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-using mwait in idle threads.\r
-CPU: Fake M5 x86_64 CPU stepping 01\r
-ACPI: Core revision 20070126\r
-ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
-ACPI: Unable to load the System Description Tables\r
-Using local APIC timer interrupts.\r
-result 7812530\r
-Detected 7.812 MHz APIC timer.\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-ACPI: Interpreter disabled.\r
-Linux Plug and Play Support v0.97 (c) Adam Belay\r
-pnp: PnP ACPI: disabled\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI->APIC IRQ transform: 0000:00:04.0[A] -> IRQ 16\r
-PCI-GART: No AMD northbridge found.\r
-NET: Registered protocol family 2\r
-Time: tsc clocksource has been installed.\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP bind hash table entries: 4096 (order: 3, 32768 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
-    ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
-    ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-PNP: No PS/2 controller found. Probing ports directly.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-NET: Registered protocol family 17\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 232k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r