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+Date: Fri, 22 May 2020 01:11:00 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords:
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-336-13-h8xJkKskcQ@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-336-13@https.bugs.libre-soc.org/>
+References: <bug-336-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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