soc/add_uart: fix bridge

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 42eab475caffe8f239ccc81d3f6663c9f788829a..c448ebf86d9932cad209d62ab450eeafe6b8bec0 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -876,7 +876,7 @@ class LiteXSoC(SoC):
                 pads     = self.platform.request("serial"),
                 clk_freq = self.sys_clk_freq,
                 baudrate = baudrate)
-            self.bus.master(name="uart_bridge", master=self.uart.wishbone)
+            self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
         elif name == "crossover":
             self.submodules.uart = uart.UARTCrossover()
         else: