layer * rtex->surface.level[level].slice_size;
}
-static int r600_init_surface(struct radeon_surface *surface,
+static int r600_init_surface(struct r600_screen *rscreen,
+ struct radeon_surface *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
bool is_transfer, bool is_flushed_depth)
surface->blk_d = 1;
surface->array_size = 1;
surface->last_level = ptex->last_level;
- surface->bpe = util_format_get_blocksize(ptex->format);
- /* align byte per element on dword */
- if (surface->bpe == 3) {
- surface->bpe = 4;
+
+ if (!is_transfer && !is_flushed_depth &&
+ ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
+ surface->bpe = 4; /* stencil is allocated separately on evergreen */
+ } else {
+ surface->bpe = util_format_get_blocksize(ptex->format);
+ /* align byte per element on dword */
+ if (surface->bpe == 3) {
+ surface->bpe = 4;
+ }
}
+
surface->nsamples = 1;
surface->flags = 0;
switch (array_mode) {
}
#endif
- r = r600_init_surface(&surface, templ, array_mode,
+ r = r600_init_surface(rscreen, &surface, templ, array_mode,
templ->flags & R600_RESOURCE_FLAG_TRANSFER,
templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
if (r) {
else
array_mode = V_009910_ARRAY_LINEAR_ALIGNED;
- r = r600_init_surface(&surface, templ, array_mode, false, false);
+ r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
if (r) {
return NULL;
}