* gencode.c (build_instruction): Work around MSVC++ code gen bug

	that messes up arithmetic shifts.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index c4f7709ca0c9a8452431ccb0eccfe1f3f9e0b405..fc6c3cfdf98cb06400f75c5cf4b3908c31dda538 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
+
+       * gencode.c (build_instruction): Work around MSVC++ code gen bug
+       that messes up arithmetic shifts.
+
 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
 
        * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for

diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c
index 023c99dd4458247f168afda68d8540935ea3d785..4f7a32703a7c50ea22bb2c6962d43a8549987ad6 100644 (file)
--- a/sim/mips/gencode.c
+++ b/sim/mips/gencode.c
@@ -1680,6 +1680,11 @@ build_instruction (doisa, features, mips16, insn)
        exit(9);
       }
 
+      /* Work around an MSC code generation bug by precomputing a value
+       * with the sign bit set.  */
+      if (insn->flags & ARITHMETIC)
+       printf("   %s highbit = (%s)1 << %d;\n", ltype, ltype, bits - 1);
+
       /* If register specified shift, then extract the relevant shift amount: */
       if (insn->flags & REG)
        printf("   op1 &= 0x%02X;\n",(bits - 1));
@@ -1701,7 +1706,7 @@ build_instruction (doisa, features, mips16, insn)
         since that would cause an undefined shift of the number of
         bits in the type.  */
       if (insn->flags & ARITHMETIC)
-       printf("   GPR[destreg] |= (op1 != 0 && (op2 & ((%s)1 << %d)) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,(bits - 1),ltype,bits);
+       printf("   GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((%s)1 << op1) - 1) << (%d - op1)) : 0);\n",ltype,bits);
 
       /* Ensure WORD values are sign-extended into 64bit registers */
       if ((bits == 32) && (gprlen == 64))