arm-arches.def: Add "armv6kz".
authorMatthew Wahab <matthew.wahab@arm.com>
Mon, 27 Jul 2015 13:07:09 +0000 (13:07 +0000)
committerMatthew Wahab <mwahab@gcc.gnu.org>
Mon, 27 Jul 2015 13:07:09 +0000 (13:07 +0000)
2015-07-27  Matthew Wahab  <matthew.wahab@arm.com>

* config/arm/arm-arches.def: Add "armv6kz". Replace 6ZK with 6KZ
and FL_FOR_ARCH6ZK with FL_FOR_ARCH6KZ.
* config/arm/arm-c.c (arm_cpu_builtins): Emit "__ARM_ARCH_6ZK__"
for armv6kz targets.
* config/arm/arm-cores.def: Replace 6ZK with 6KZ.
* config/arm/arm-protos.h (FL_ARCH6KZ): New.
(FL_FOR_ARCH6ZK): Remove.
(FL_FOR_ARCH6KZ): New.
(arm_arch6zk): New declaration.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (arm_arch6kz): New.
(arm_option_override): Set arm_arch6kz.
* config/arm/arm.h (BASE_ARCH_6ZK): Rename to BASE_ARCH_6KZ.
* config/arm/driver-arm.c: Add comment to "armv6zk" entry.
        * doc/invoke.texi: Replace "armv6zk" with "armv6kz".

From-SVN: r226243

gcc/ChangeLog
gcc/config/arm/arm-arches.def
gcc/config/arm/arm-c.c
gcc/config/arm/arm-cores.def
gcc/config/arm/arm-protos.h
gcc/config/arm/arm-tables.opt
gcc/config/arm/arm.c
gcc/config/arm/arm.h
gcc/config/arm/driver-arm.c
gcc/doc/invoke.texi

index 177f71c87386fa9a4a53e94e0466737d3d7c4f46..0a9ae7fef8813c60a80f90a6d37111b92b832cbc 100644 (file)
@@ -1,3 +1,21 @@
+2015-07-27  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * config/arm/arm-arches.def: Add "armv6kz". Replace 6ZK with 6KZ
+       and FL_FOR_ARCH6ZK with FL_FOR_ARCH6KZ.
+       * config/arm/arm-c.c (arm_cpu_builtins): Emit "__ARM_ARCH_6ZK__"
+       for armv6kz targets.
+       * config/arm/arm-cores.def: Replace 6ZK with 6KZ.
+       * config/arm/arm-protos.h (FL_ARCH6KZ): New.
+       (FL_FOR_ARCH6ZK): Remove.
+       (FL_FOR_ARCH6KZ): New.
+       (arm_arch6zk): New declaration.
+       * config/arm/arm-tables.opt: Regenerate.
+       * config/arm/arm.c (arm_arch6kz): New.
+       (arm_option_override): Set arm_arch6kz.
+       * config/arm/arm.h (BASE_ARCH_6ZK): Rename to BASE_ARCH_6KZ.
+       * config/arm/driver-arm.c: Add comment to "armv6zk" entry.
+        * doc/invoke.texi: Replace "armv6zk" with "armv6kz".
+
 2015-07-27  Marek Polacek  <polacek@redhat.com>
 
        PR c++/66555
index 840c1ff4be8df7e1faf3a1fdb290824e789a6ac0..3dafaa5fbc80af4b8d5004a2b53be3de01e6b9eb 100644 (file)
@@ -44,7 +44,8 @@ ARM_ARCH("armv6",   arm1136js,  6,   FL_CO_PROC |             FL_FOR_ARCH6)
 ARM_ARCH("armv6j",  arm1136js,  6J,  FL_CO_PROC |             FL_FOR_ARCH6J)
 ARM_ARCH("armv6k",  mpcore,    6K,  FL_CO_PROC |             FL_FOR_ARCH6K)
 ARM_ARCH("armv6z",  arm1176jzs, 6Z,  FL_CO_PROC |             FL_FOR_ARCH6Z)
-ARM_ARCH("armv6zk", arm1176jzs, 6ZK, FL_CO_PROC |             FL_FOR_ARCH6ZK)
+ARM_ARCH("armv6kz", arm1176jzs, 6KZ, FL_CO_PROC |             FL_FOR_ARCH6KZ)
+ARM_ARCH("armv6zk", arm1176jzs, 6KZ, FL_CO_PROC |             FL_FOR_ARCH6KZ)
 ARM_ARCH("armv6t2", arm1156t2s, 6T2, FL_CO_PROC |             FL_FOR_ARCH6T2)
 ARM_ARCH("armv6-m", cortexm1,  6M,                           FL_FOR_ARCH6M)
 ARM_ARCH("armv6s-m", cortexm1, 6M,                           FL_FOR_ARCH6M)
index 297995b810009f944d5cd878bd1731b9c1c0ea8f..9bf3973f2905ab76625d27e7c544c86efc12414c 100644 (file)
@@ -167,6 +167,11 @@ arm_cpu_builtins (struct cpp_reader* pfile, int flags)
     }
   if (arm_arch_iwmmxt2)
     builtin_define ("__IWMMXT2__");
+  /* ARMv6KZ was originally identified as the misspelled __ARM_ARCH_6ZK__.  To
+     preserve the existing behaviour, the misspelled feature macro must still be
+     defined.  */
+  if (arm_arch6kz)
+    builtin_define ("__ARM_ARCH_6ZK__");
   if (TARGET_AAPCS_BASED)
     {
       if (arm_pcs_default == ARM_PCS_AAPCS_VFP)
index 103c3140514b31afd7f80e17bdc742779f53bf4f..9d47fcfbcd7ef28ac5cfaa3791c87e5f6d84dc69 100644 (file)
@@ -125,8 +125,8 @@ ARM_CORE("arm1026ej-s",     arm1026ejs, arm1026ejs, 5TEJ, FL_LDSCHED, 9e)
 /* V6 Architecture Processors */
 ARM_CORE("arm1136j-s",         arm1136js, arm1136js,           6J,  FL_LDSCHED, 9e)
 ARM_CORE("arm1136jf-s",                arm1136jfs, arm1136jfs,         6J,  FL_LDSCHED | FL_VFPV2, 9e)
-ARM_CORE("arm1176jz-s",                arm1176jzs, arm1176jzs,         6ZK, FL_LDSCHED, 9e)
-ARM_CORE("arm1176jzf-s",       arm1176jzfs, arm1176jzfs,       6ZK, FL_LDSCHED | FL_VFPV2, 9e)
+ARM_CORE("arm1176jz-s",                arm1176jzs, arm1176jzs,         6KZ, FL_LDSCHED, 9e)
+ARM_CORE("arm1176jzf-s",       arm1176jzfs, arm1176jzfs,       6KZ, FL_LDSCHED | FL_VFPV2, 9e)
 ARM_CORE("mpcorenovfp",                mpcorenovfp, mpcorenovfp,       6K,  FL_LDSCHED, 9e)
 ARM_CORE("mpcore",             mpcore, mpcore,                 6K,  FL_LDSCHED | FL_VFPV2, 9e)
 ARM_CORE("arm1156t2-s",                arm1156t2s, arm1156t2s,         6T2, FL_LDSCHED, v6t2)
index 62f91efc0ad62f1e88d00c6fd3702e2a0fbc470e..7aae9343e026b3b1f15fae0c13daabe003696c91 100644 (file)
@@ -382,6 +382,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 
 #define FL_IWMMXT     (1 << 29)              /* XScale v2 or "Intel Wireless MMX technology".  */
 #define FL_IWMMXT2    (1 << 30)       /* "Intel Wireless MMX2 technology".  */
+#define FL_ARCH6KZ    (1 << 31)       /* ARMv6KZ architecture.  */
 
 /* Flags that only effect tuning, not available instructions.  */
 #define FL_TUNE                (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
@@ -401,7 +402,7 @@ extern bool arm_is_constant_pool_ref (rtx);
 #define FL_FOR_ARCH6J  FL_FOR_ARCH6
 #define FL_FOR_ARCH6K  (FL_FOR_ARCH6 | FL_ARCH6K)
 #define FL_FOR_ARCH6Z  FL_FOR_ARCH6
-#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
+#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
 #define FL_FOR_ARCH6M  (FL_FOR_ARCH6 & ~FL_NOTM)
 #define FL_FOR_ARCH7   ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
@@ -441,6 +442,9 @@ extern int arm_arch6;
 /* Nonzero if this chip supports the ARM 6K extensions.  */
 extern int arm_arch6k;
 
+/* Nonzero if this chip supports the ARM 6KZ extensions.  */
+extern int arm_arch6kz;
+
 /* Nonzero if instructions present in ARMv6-M can be used.  */
 extern int arm_arch6m;
 
index 510e745611904a06e368dd0b5cc3835fe1406f08..77e44aac0b84ed720fa6873382a316f41c373984 100644 (file)
@@ -371,46 +371,49 @@ EnumValue
 Enum(arm_arch) String(armv6z) Value(13)
 
 EnumValue
-Enum(arm_arch) String(armv6zk) Value(14)
+Enum(arm_arch) String(armv6kz) Value(14)
 
 EnumValue
-Enum(arm_arch) String(armv6t2) Value(15)
+Enum(arm_arch) String(armv6zk) Value(15)
 
 EnumValue
-Enum(arm_arch) String(armv6-m) Value(16)
+Enum(arm_arch) String(armv6t2) Value(16)
 
 EnumValue
-Enum(arm_arch) String(armv6s-m) Value(17)
+Enum(arm_arch) String(armv6-m) Value(17)
 
 EnumValue
-Enum(arm_arch) String(armv7) Value(18)
+Enum(arm_arch) String(armv6s-m) Value(18)
 
 EnumValue
-Enum(arm_arch) String(armv7-a) Value(19)
+Enum(arm_arch) String(armv7) Value(19)
 
 EnumValue
-Enum(arm_arch) String(armv7ve) Value(20)
+Enum(arm_arch) String(armv7-a) Value(20)
 
 EnumValue
-Enum(arm_arch) String(armv7-r) Value(21)
+Enum(arm_arch) String(armv7ve) Value(21)
 
 EnumValue
-Enum(arm_arch) String(armv7-m) Value(22)
+Enum(arm_arch) String(armv7-r) Value(22)
 
 EnumValue
-Enum(arm_arch) String(armv7e-m) Value(23)
+Enum(arm_arch) String(armv7-m) Value(23)
 
 EnumValue
-Enum(arm_arch) String(armv8-a) Value(24)
+Enum(arm_arch) String(armv7e-m) Value(24)
 
 EnumValue
-Enum(arm_arch) String(armv8-a+crc) Value(25)
+Enum(arm_arch) String(armv8-a) Value(25)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(26)
+Enum(arm_arch) String(armv8-a+crc) Value(26)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(27)
+Enum(arm_arch) String(iwmmxt) Value(27)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(28)
 
 Enum
 Name(arm_fpu) Type(int)
index eeab8a8b5ae318e29845ec0f13f394e48a9464bb..c737484313ab8e9c1526540a2ec40dd7b5acd043 100644 (file)
@@ -801,6 +801,9 @@ int arm_arch6 = 0;
 /* Nonzero if this chip supports the ARM 6K extensions.  */
 int arm_arch6k = 0;
 
+/* Nonzero if this chip supports the ARM 6KZ extensions.  */
+int arm_arch6kz = 0;
+
 /* Nonzero if instructions present in ARMv6-M can be used.  */
 int arm_arch6m = 0;
 
@@ -3043,6 +3046,7 @@ arm_option_override (void)
   arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
   arm_arch6 = (insn_flags & FL_ARCH6) != 0;
   arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
+  arm_arch6kz = arm_arch6k && (insn_flags & FL_ARCH6KZ);
   arm_arch_notm = (insn_flags & FL_NOTM) != 0;
   arm_arch6m = arm_arch6 && !arm_arch_notm;
   arm_arch7 = (insn_flags & FL_ARCH7) != 0;
index 836e5179d9b195ba416d506617115b94d8b595c8..bb64be00c12842bfe67a0d2218fa770cc533302b 100644 (file)
@@ -374,7 +374,7 @@ enum base_architecture
   BASE_ARCH_5TEJ = 5,
   BASE_ARCH_6 = 6,
   BASE_ARCH_6J = 6,
-  BASE_ARCH_6ZK = 6,
+  BASE_ARCH_6KZ = 6,
   BASE_ARCH_6K = 6,
   BASE_ARCH_6T2 = 6,
   BASE_ARCH_6M = 6,
index c715bb7c11749711224781362a83b00891313950..9d24a3fb3780aca76b13cabc297f8f87b061a537 100644 (file)
@@ -35,6 +35,9 @@ static struct vendor_cpu arm_cpu_table[] = {
     {"0xb02", "armv6k", "mpcore"},
     {"0xb36", "armv6j", "arm1136j-s"},
     {"0xb56", "armv6t2", "arm1156t2-s"},
+    /* armv6kz is the correct spelling for ARMv6KZ but may not be supported in
+       the version of binutils used.  The incorrect spelling is supported in
+       legacy and current binutils so that is used instead.  */
     {"0xb76", "armv6zk", "arm1176jz-s"},
     {"0xc05", "armv7-a", "cortex-a5"},
     {"0xc07", "armv7ve", "cortex-a7"},
index e988444bdb71b6fcbd8332b8294af3a5dc4cb0d5..7b5d86b62bb633d7382743d50587187438f06f80 100644 (file)
@@ -13319,7 +13319,7 @@ of the @option{-mcpu=} option.  Permissible names are: @samp{armv2},
 @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
 @samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
 @samp{armv6}, @samp{armv6j},
-@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m},
+@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
 @samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
 @samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc},
 @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.