GHDLFLAGS=--std=08
CFLAGS=-O3 -Wall
# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
-VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT #--trace
+VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT
+VERILATOR_TRACE=0
+
+ifeq ($(VERILATOR_TRACE),1)
+VERILATOR_FLAGS += --trace
+verilator_extra_link = -Wl,obj_dir/verilated_vcd_c.o
+endif
+
# It takes forever to build with optimisation, so disable by default
#VERILATOR_CFLAGS=-O3
make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
SIM_DRAM_CFLAGS = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
-SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new
+SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=$(VERILATOR_TRACE) -DVL_PRINTF=printf -faligned-new
sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
-dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++
+dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o $(verilator_extra_link) -Wl,-lstdc++
soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
$(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
MEMORY_SIZE : natural := (384*1024);
MAIN_RAM_FILE : string := "main_ram.bin";
DRAM_INIT_FILE : string := "";
- DRAM_INIT_SIZE : natural := 16#c000#
+ DRAM_INIT_SIZE : natural := 16#c000#;
+ L2_TRACE : boolean := false;
+ LITEDRAM_TRACE : boolean := false
);
end core_dram_tb;
DRAM_CKLINES => 1,
DRAM_PORT_WIDTH => 128,
PAYLOAD_FILE => DRAM_INIT_FILE,
- PAYLOAD_SIZE => ROM_SIZE
+ PAYLOAD_SIZE => ROM_SIZE,
+ TRACE => L2_TRACE,
+ LITEDRAM_TRACE => LITEDRAM_TRACE
)
port map(
clk_in => clk,
entity dram_tb is
generic (
DRAM_INIT_FILE : string := "";
- DRAM_INIT_SIZE : natural := 0
+ DRAM_INIT_SIZE : natural := 0;
+ L2_TRACE : boolean := false;
+ LITEDRAM_TRACE : boolean := false
);
end dram_tb;
DRAM_CKLINES => 1,
DRAM_PORT_WIDTH => 128,
PAYLOAD_FILE => DRAM_INIT_FILE,
- PAYLOAD_SIZE => DRAM_INIT_SIZE
+ PAYLOAD_SIZE => DRAM_INIT_SIZE,
+ TRACE => L2_TRACE,
+ LITEDRAM_TRACE => LITEDRAM_TRACE
)
port map(
clk_in => clk_in,