test_sim: add missing add_process().

Fixes #43.

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index 6a09a5b21229ca6f8947521b8be228f1fd2fdcfb..ff3986d751b12121661322fa1ad57a5a217dae8f 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -376,9 +376,10 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
         with self.assertSimulation(Module(), deadline=100e-6) as sim:
             sim.add_clock(1e-6)
             def process():
-                for _ in range(100):
-                    yield
+                for _ in range(101):
+                    yield Delay(1e-6)
                 self.fail()
+            sim.add_process(process)
 
     def test_add_process_wrong(self):
         with self.assertSimulation(Module()) as sim: