print out reg num in _check_regs, useful debug

diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py
index 23db0a9614f4c307175d68adbc68973f64b063af..ba6906b41345e7b691f837994f6c145c77ce4bb2 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_predication.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py
@@ -19,7 +19,9 @@ class DecoderTestCase(FHDLTestCase):
 
     def _check_regs(self, sim, expected):
         for i in range(32):
-            self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
+            self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
+                             "reg %d expected %x got %x" % \
+                            (i, sim.gpr(i).value, expected[i]))
 
     def tst_sv_load_store(self):
         lst = SVP64Asm(["addi 1, 0, 0x0010",