[ARM] Tie operand 1 to operand 0 in AESMC pattern when fusing AES/AESMC

	* config/arm/arm.c (arm_fusion_enabled_p): New function.
	* config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
	* config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
	Add "=w,0" alternative.  Enable it when AES/AESMC fusion is enabled.

From-SVN: r236982

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 83a96bd5dc5c5aab4f48cf17cdc3cb664638f9b1..b9baf4c9c0a85c9cacc1f0061baad4d2ef1d39ef 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/arm.c (arm_fusion_enabled_p): New function.
+       * config/arm/arm-protos.h (arm_fusion_enabled_p): Declare prototype.
+       * config/arm/crypto.md (crypto_<crypto_pattern>, CRYPTO_UNARY):
+       Add "=w,0" alternative.  Enable it when AES/AESMC fusion is enabled.
+
 2016-06-01  Eric Botcazou  <ebotcazou@adacore.com>
 
        * tree-vect-loop.c (vect_determine_vectorization_factor): Also take

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 34fd06a92d99cfcb7ece4da7f1a2957e0225e4fb..aaaabb761cfdad943ac895b511a0514cd4ee8471 100644 (file)
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -321,6 +321,7 @@ extern int vfp3_const_double_for_bits (rtx);
 
 extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx,
                                           rtx);
+extern bool arm_fusion_enabled_p (tune_params::fuse_ops);
 extern bool arm_valid_symbolic_address_p (rtx);
 extern bool arm_validize_comparison (rtx *, rtx *, rtx *);
 #endif /* RTX_CODE */

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 16499ce647bba0adc2fdb4b8f7d665b169deb4e7..e9240908ea9c7795f1064f6741091eb3264ef0ff 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -29858,6 +29858,13 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
   return false;
 }
 
+/* Return true iff the instruction fusion described by OP is enabled.  */
+bool
+arm_fusion_enabled_p (tune_params::fuse_ops op)
+{
+  return current_tune->fusible_ops & op;
+}
+
 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook.  */
 
 static unsigned HOST_WIDE_INT

diff --git a/gcc/config/arm/crypto.md b/gcc/config/arm/crypto.md
index c6f17270b1dbaf6dc43eb1e9b8a182dbb0f5a1e1..0f510f069408471fcbf6751f161e984f39929813 100644 (file)
--- a/gcc/config/arm/crypto.md
+++ b/gcc/config/arm/crypto.md
@@ -18,14 +18,27 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
+
+;; When AES/AESMC fusion is enabled we want the register allocation to
+;; look like:
+;;    AESE Vn, _
+;;    AESMC Vn, Vn
+;; So prefer to tie operand 1 to operand 0 when fusing.
+
 (define_insn "crypto_<crypto_pattern>"
-  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w")
+  [(set (match_operand:<crypto_mode> 0 "register_operand" "=w,w")
         (unspec:<crypto_mode> [(match_operand:<crypto_mode> 1
-                       "register_operand" "w")]
+                       "register_operand" "0,w")]
          CRYPTO_UNARY))]
   "TARGET_CRYPTO"
   "<crypto_pattern>.<crypto_size_sfx>\\t%q0, %q1"
-  [(set_attr "type" "<crypto_type>")]
+  [(set_attr "type" "<crypto_type>")
+   (set_attr_alternative "enabled"
+     [(if_then_else (match_test
+                      "arm_fusion_enabled_p (tune_params::FUSE_AES_AESMC)")
+                    (const_string "yes" )
+                    (const_string "no"))
+      (const_string "yes")])]
 )
 
 (define_insn "crypto_<crypto_pattern>"