using namespace llvm;
-AMDGPURegisterInfo::AMDGPURegisterInfo(AMDGPUTargetMachine &tm,
+AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
-: AMDILRegisterInfo(tm, tii),
+: AMDGPUGenRegisterInfo(0),
TM(tm),
TII(tii)
{ }
+
+//===----------------------------------------------------------------------===//
+// Function handling callbacks - Functions are a seldom used feature of GPUS, so
+// they are not supported at this time.
+//===----------------------------------------------------------------------===//
+
+const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
+
+const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
+ const {
+ return &CalleeSavedReg;
+}
+
+void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
+ int SPAdj,
+ RegScavenger *RS) const {
+ assert(!"Subroutines not supported yet");
+}
+
+unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+ assert(!"Subroutines not supported yet");
+ return 0;
+}
+
+#define GET_REGINFO_TARGET_DESC
+#include "AMDGPUGenRegisterInfo.inc"
#ifndef AMDGPUREGISTERINFO_H_
#define AMDGPUREGISTERINFO_H_
-#include "AMDILRegisterInfo.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#define GET_REGINFO_ENUM
+#include "AMDGPUGenRegisterInfo.inc"
namespace llvm {
class AMDGPUTargetMachine;
class TargetInstrInfo;
-struct AMDGPURegisterInfo : public AMDILRegisterInfo
+struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo
{
- AMDGPUTargetMachine &TM;
+ TargetMachine &TM;
const TargetInstrInfo &TII;
+ static const uint16_t CalleeSavedReg;
- AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
- virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const {
+ assert(!"Unimplemented"); return BitVector();
+ }
/// getISARegClass - rc is an AMDIL reg class. This function returns the
/// ISA reg class that is equivalent to the given AMDIL reg class.
- virtual const TargetRegisterClass *
- getISARegClass(const TargetRegisterClass * rc) const = 0;
+ virtual const TargetRegisterClass * getISARegClass(
+ const TargetRegisterClass * rc) const {
+ assert(!"Unimplemented"); return NULL;
+ }
+
+ virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
+ assert(!"Unimplemented"); return NULL;
+ }
+
+ const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+ RegScavenger *RS) const;
+ unsigned getFrameRegister(const MachineFunction &MF) const;
+
};
} // End namespace llvm
extern Target TheAMDGPUTarget;
} // end namespace llvm;
-#define GET_REGINFO_ENUM
-#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "AMDGPUGenInstrInfo.inc"
#include "AMDIL.h"
#include "AMDILInstrInfo.h"
-#include "AMDILRegisterInfo.h"
#include "AMDILUtilityFunctions.h"
#include "llvm/ADT/SCCIterator.h"
#include "llvm/ADT/SmallVector.h"
~CFGStructurizer();
/// Perform the CFG structurization
- bool run(FuncT &Func, PassT &Pass, const AMDILRegisterInfo *tri);
+ bool run(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri);
/// Perform the CFG preparation
- bool prepare(FuncT &Func, PassT &Pass, const AMDILRegisterInfo *tri);
+ bool prepare(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri);
private:
void orderBlocks();
BlockInfoMap blockInfoMap;
LoopLandInfoMap loopLandInfoMap;
SmallVector<BlockT *, DEFAULT_VEC_SLOTS> orderedBlks;
- const AMDILRegisterInfo *TRI;
+ const AMDGPURegisterInfo *TRI;
}; //template class CFGStructurizer
template<class PassT>
bool CFGStructurizer<PassT>::prepare(FuncT &func, PassT &pass,
- const AMDILRegisterInfo * tri) {
+ const AMDGPURegisterInfo * tri) {
passRep = &pass;
funcRep = &func;
TRI = tri;
template<class PassT>
bool CFGStructurizer<PassT>::run(FuncT &func, PassT &pass,
- const AMDILRegisterInfo * tri) {
+ const AMDGPURegisterInfo * tri) {
passRep = &pass;
funcRep = &func;
TRI = tri;
protected:
TargetMachine &TM;
const TargetInstrInfo *TII;
- const AMDILRegisterInfo *TRI;
+ const AMDGPURegisterInfo *TRI;
public:
AMDILCFGStructurizer(char &pid, TargetMachine &tm AMDIL_OPT_LEVEL_DECL);
AMDILCFGStructurizer::AMDILCFGStructurizer(char &pid, TargetMachine &tm
AMDIL_OPT_LEVEL_DECL)
: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
- TRI(static_cast<const AMDILRegisterInfo *>(tm.getRegisterInfo())
+ TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())
) {
}
//
//===----------------------------------------------------------------------===//
#include "AMDGPUISelLowering.h" // For AMDGPUISD
+#include "AMDGPURegisterInfo.h"
#include "AMDILDevices.h"
#include "AMDILUtilityFunctions.h"
#include "llvm/ADT/ValueMap.h"
//===----------------------------------------------------------------------===//
#include "AMDILISelLowering.h"
+#include "AMDGPURegisterInfo.h"
#include "AMDILDevices.h"
#include "AMDILIntrinsicInfo.h"
-#include "AMDILRegisterInfo.h"
#include "AMDILSubtarget.h"
#include "AMDILUtilityFunctions.h"
#include "llvm/CallingConv.h"
TM(tm) {
}
-const AMDILRegisterInfo &AMDILInstrInfo::getRegisterInfo() const {
+const AMDGPURegisterInfo &AMDILInstrInfo::getRegisterInfo() const {
return RI;
}
#ifndef AMDILINSTRUCTIONINFO_H_
#define AMDILINSTRUCTIONINFO_H_
-#include "AMDILRegisterInfo.h"
+#include "AMDGPURegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
//class AMDILTargetMachine;
class AMDILInstrInfo : public AMDGPUGenInstrInfo {
private:
- const AMDILRegisterInfo RI;
+ const AMDGPURegisterInfo RI;
TargetMachine &TM;
bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
MachineBasicBlock &MBB) const;
// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
// such, whenever a client has an instance of instruction info, it should
// always be able to get register info as well (through this method).
- const AMDILRegisterInfo &getRegisterInfo() const;
+ const AMDGPURegisterInfo &getRegisterInfo() const;
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
unsigned &DstReg, unsigned &SubIdx) const;
+++ /dev/null
-//===- AMDILRegisterInfo.cpp - AMDIL Register Information -------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the AMDIL implementation of the TargetRegisterInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AMDILRegisterInfo.h"
-#include "AMDIL.h"
-#include "AMDILInstrInfo.h"
-#include "llvm/ADT/BitVector.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-using namespace llvm;
-
-AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm,
- const TargetInstrInfo &tii)
-: AMDGPUGenRegisterInfo(0), // RA???
- TM(tm), TII(tii)
-{
- baseOffset = 0;
- nextFuncOffset = 0;
-}
-
-const uint16_t*
-AMDILRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
-{
- static const uint16_t CalleeSavedRegs[] = { 0 };
- // TODO: Does IL need to actually have any callee saved regs?
- // I don't think we do since we can just use sequential registers
- // Maybe this would be easier if every function call was inlined first
- // and then there would be no callee issues to deal with
- //TODO(getCalleeSavedRegs);
- return CalleeSavedRegs;
-}
-
-BitVector
-AMDILRegisterInfo::getReservedRegs(const MachineFunction &MF) const
-{
- BitVector Reserved(getNumRegs());
- // We reserve the first getNumRegs() registers as they are the ones passed
- // in live-in/live-out
- // and therefor cannot be killed by the scheduler. This works around a bug
- // discovered
- // that was causing the linearscan register allocator to kill registers
- // inside of the
- // function that were also passed as LiveIn registers.
- for (unsigned int x = 0, y = 256; x < y; ++x) {
- Reserved.set(x);
- }
- return Reserved;
-}
-
-BitVector
-AMDILRegisterInfo::getAllocatableSet(const MachineFunction &MF,
- const TargetRegisterClass *RC = NULL) const
-{
- BitVector Allocatable(getNumRegs());
- Allocatable.clear();
- return Allocatable;
-}
-
-const TargetRegisterClass* const*
-AMDILRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
-{
- static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
- // TODO: Keep in sync with getCalleeSavedRegs
- //TODO(getCalleeSavedRegClasses);
- return CalleeSavedRegClasses;
-}
-void
-AMDILRegisterInfo::eliminateCallFramePseudoInstr(
- MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const
-{
- MBB.erase(I);
-}
-
-// For each frame index we find, we store the offset in the stack which is
-// being pushed back into the global buffer. The offset into the stack where
-// the value is stored is copied into a new register and the frame index is
-// then replaced with that register.
-void
-AMDILRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj,
- RegScavenger *RS) const
-{
- assert(!"Implement");
-}
-
-void
-AMDILRegisterInfo::processFunctionBeforeFrameFinalized(
- MachineFunction &MF) const
-{
- //TODO(processFunctionBeforeFrameFinalized);
- // Here we keep track of the amount of stack that the current function
- // uses so
- // that we can set the offset to the end of the stack and any other
- // function call
- // will not overwrite any stack variables.
- // baseOffset = nextFuncOffset;
- MachineFrameInfo *MFI = MF.getFrameInfo();
-
- for (uint32_t x = 0, y = MFI->getNumObjects(); x < y; ++x) {
- int64_t size = MFI->getObjectSize(x);
- if (!(size % 4) && size > 1) {
- nextFuncOffset += size;
- } else {
- nextFuncOffset += 16;
- }
- }
-}
-unsigned int
-AMDILRegisterInfo::getRARegister() const
-{
- return AMDGPU::RA;
-}
-
-unsigned int
-AMDILRegisterInfo::getFrameRegister(const MachineFunction &MF) const
-{
- return AMDGPU::FP;
-}
-
-unsigned int
-AMDILRegisterInfo::getEHExceptionRegister() const
-{
- assert(0 && "What is the exception register");
- return 0;
-}
-
-unsigned int
-AMDILRegisterInfo::getEHHandlerRegister() const
-{
- assert(0 && "What is the exception handler register");
- return 0;
-}
-
-int64_t
-AMDILRegisterInfo::getStackSize() const
-{
- return nextFuncOffset - baseOffset;
-}
-
-#define GET_REGINFO_TARGET_DESC
-#include "AMDGPUGenRegisterInfo.inc"
-
+++ /dev/null
-//===- AMDILRegisterInfo.h - AMDIL Register Information Impl ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//==-----------------------------------------------------------------------===//
-//
-// This file contains the AMDIL implementation of the TargetRegisterInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef AMDILREGISTERINFO_H_
-#define AMDILREGISTERINFO_H_
-
-#include "llvm/Target/TargetRegisterInfo.h"
-
-#define GET_REGINFO_HEADER
-#include "AMDGPUGenRegisterInfo.inc"
-// See header file for explanation
-
-namespace llvm
-{
-
- class TargetInstrInfo;
- class Type;
-
- /// DWARFFlavour - Flavour of dwarf regnumbers
- ///
- namespace DWARFFlavour {
- enum {
- AMDIL_Generic = 0
- };
- }
-
- struct AMDILRegisterInfo : public AMDGPUGenRegisterInfo
- {
- TargetMachine &TM;
- const TargetInstrInfo &TII;
-
- AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
- /// Code Generation virtual methods...
- const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const;
-
- const TargetRegisterClass* const*
- getCalleeSavedRegClasses(
- const MachineFunction *MF = 0) const;
-
- BitVector
- getReservedRegs(const MachineFunction &MF) const;
- BitVector
- getAllocatableSet(const MachineFunction &MF,
- const TargetRegisterClass *RC) const;
-
- void
- eliminateCallFramePseudoInstr(
- MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const;
- void
- eliminateFrameIndex(MachineBasicBlock::iterator II,
- int SPAdj, RegScavenger *RS = NULL) const;
-
- void
- processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
-
- // Debug information queries.
- unsigned int
- getRARegister() const;
-
- unsigned int
- getFrameRegister(const MachineFunction &MF) const;
-
- // Exception handling queries.
- unsigned int
- getEHExceptionRegister() const;
- unsigned int
- getEHHandlerRegister() const;
-
- int64_t
- getStackSize() const;
-
- virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT)
- const {
- return AMDGPU::GPRI32RegisterClass;
- }
- private:
- mutable int64_t baseOffset;
- mutable int64_t nextFuncOffset;
- };
-
-} // end namespace llvm
-
-#endif // AMDILREGISTERINFO_H_
AMDILISelLowering.cpp \
AMDILNIDevice.cpp \
AMDILPeepholeOptimizer.cpp \
- AMDILRegisterInfo.cpp \
AMDILSIDevice.cpp \
AMDILSubtarget.cpp \
AMDGPUSubtarget.cpp \
#define R600REGISTERINFO_H_
#include "AMDGPUTargetMachine.h"
-#include "AMDILRegisterInfo.h"
+#include "AMDGPURegisterInfo.h"
namespace llvm {
projects / mesa.git / commitdiff