soc,cpuif: support user defined constants

diff --git a/make.py b/make.py
index 43e4d293fa29b2c9908acf2fc86a394a06a26b9c..6591ceee4f809423c1d045dcde717b82eba26cc8 100755 (executable)
--- a/make.py
+++ b/make.py
@@ -162,7 +162,7 @@ CPU type:  {}
                                        write_to_file(os.path.join(genhdir, "sdram_phy.h"), boilerplate + sdram_phy_header)
                mem_header = cpuif.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None))
                write_to_file(os.path.join(genhdir, "mem.h"), boilerplate + mem_header)
-               csr_header = cpuif.get_csr_header(csr_regions, soc.interrupt_map)
+               csr_header = cpuif.get_csr_header(csr_regions, soc.get_constants())
                write_to_file(os.path.join(genhdir, "csr.h"), boilerplate + csr_header)
 
        if actions["build-csr-csv"]:

diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index f900dac9147454d64aa6a678b70dccafc33804bc..ada3e9e4e01a42c34154d8017c6ddde0f54c74d9 100644 (file)
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -64,6 +64,7 @@ class SoC(Module):
 
                self._memory_regions = [] # list of (name, origin, length)
                self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
+               self._constants = [] # list of (name, value)
 
                self._wb_masters = []
                self._wb_slaves = []
@@ -159,6 +160,16 @@ class SoC(Module):
        def get_csr_regions(self):
                return self._csr_regions
 
+       def add_constant(self, name, value):
+               self._constants.append((name, value))
+
+       def get_constants(self):
+               r = []
+               for name, interrupt in sorted(self.interrupt_map.items(), key=itemgetter(1)):
+                       r.append((name.upper() + "_INTERRUPT", interrupt))
+               r += self._constants
+               return r
+
        def do_finalize(self):
                registered_mems = {regions[0] for regions in self._memory_regions}
                if self.cpu_type != "none":

diff --git a/misoclib/soc/cpuif.py b/misoclib/soc/cpuif.py
index 737d2c71a432a96448496dfb921e4bc702180bf0..48d77604ed5bcf1bd79a2a6bce9ec0298db6b218 100644 (file)
--- a/misoclib/soc/cpuif.py
+++ b/misoclib/soc/cpuif.py
@@ -68,7 +68,7 @@ def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
                r += "}\n"
        return r
 
-def get_csr_header(regions, interrupt_map):
+def get_csr_header(regions, constants):
        r = "#ifndef __GENERATED_CSR_H\n#define __GENERATED_CSR_H\n#include <hw/common.h>\n"
        for name, origin, busword, obj in regions:
                if isinstance(obj, Memory):
@@ -80,12 +80,11 @@ def get_csr_header(regions, interrupt_map):
                                nr = (csr.size + busword - 1)//busword
                                r += _get_rw_functions(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus))
                                origin += 4*nr
-                       try:
-                               interrupt_nr = interrupt_map[name]
-                       except KeyError:
-                               pass
-                       else:
-                               r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
+
+       r += "\n/* constants */\n"
+       for name, value in constants:
+               r += "#define " + name + " " + str(value) + "\n"
+
        r += "\n#endif\n"
        return r