.gitmodules: use our VexRiscv-verilog

diff --git a/.gitmodules b/.gitmodules
index 584a052deda78caea68496cf3b7b355a2ed9b618..89798374bb26a85a1f8e04415f42eb7c5b0779cb 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -15,4 +15,4 @@
        url = https://github.com/enjoy-digital/tapcfg
 [submodule "litex/soc/cores/cpu/vexriscv/verilog"]
        path = litex/soc/cores/cpu/vexriscv/verilog
-       url = https://github.com/m-labs/VexRiscv-verilog.git
+       url = https://github.com/enjoy-digital/VexRiscv-verilog.git

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index ebe4064653bc143bf92a0ccdd1099173620fcbf5..66faa6ece6551abac424146f9a27960ba10f4cf8 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5
+Subproject commit 66faa6ece6551abac424146f9a27960ba10f4cf8