ecp5: Fixing miscellaneous sim model issues

Signed-off-by: David Shah <davey1576@gmail.com>

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index cf1446a52d428f3b036ef82899c7eb450fa85e1a..1700694e8c412abca4e4b5a61ae5f64449b173e9 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
                        always @(posedge muxclk, posedge muxlsr)
                                if (muxlsr)
                                        Q <= srval;
-                               else
+                               else if (muxce)
                                        Q <= DI;
                end else begin
                        always @(posedge muxclk)
                                if (muxlsr)
                                        Q <= srval;
-                               else
+                               else if (muxce)
                                        Q <= DI;
                end
        endgenerate