#define REG_SP 13
#define REG_LR 14
#define REG_PC 15
+#define REG_RA_AUTH_CODE 143
/* ARM instructions take 4bytes in the object file, Thumb instructions
take 2: */
reg = arm_reg_parse (&str, rt);
- /* Skip over allowed registers of alternative types in mixed-type
- register lists. */
- if (reg == FAIL && rt == REG_TYPE_PSEUDO
- && ((reg = arm_reg_parse (&str, REG_TYPE_RN)) != FAIL))
- {
- cur_reg = reg;
- continue;
- }
- else if (reg == FAIL && rt == REG_TYPE_RN
- && ((reg = arm_reg_parse (&str, REG_TYPE_PSEUDO)) != FAIL))
- {
- cur_reg = reg;
- continue;
- }
-
if (etype == REGLIST_CLRM)
{
if (reg == REG_SP || reg == REG_PC)
unwind.sp_restored = 0;
}
-
/* Parse a handlerdata directive. Creates the exception handling table entry
for the function. */
/* Parse a directive saving pseudo registers. */
static void
-s_arm_unwind_save_pseudo (long range)
+s_arm_unwind_save_pseudo (int regno)
{
valueT op;
- if (range & (1 << 12))
+ switch (regno)
{
+ case REG_RA_AUTH_CODE:
/* Opcode for restoring RA_AUTH_CODE. */
op = 0xb4;
add_unwind_opcode (op, 1);
+ break;
+ default:
+ as_bad (_("Unknown register no. encountered: %d\n"), regno);
}
}
}
}
+/* Implement correct handling of .save lists enabling the split into
+sublists where necessary, while preserving correct sublist ordering. */
+
+static void
+parse_dot_save (char **str_p, int prev_reg)
+{
+ long core_regs = 0;
+ int reg;
+ int in_range = 0;
+
+ if (**str_p == ',')
+ *str_p += 1;
+ if (**str_p == '}')
+ {
+ *str_p += 1;
+ return;
+ }
+
+ while ((reg = arm_reg_parse (str_p, REG_TYPE_RN)) != FAIL)
+ {
+ if (!in_range)
+ {
+ if (core_regs & (1 << reg))
+ as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
+ reg);
+ else if (reg <= prev_reg)
+ as_tsktsk (_("Warning: register list not in ascending order"));
+
+ core_regs |= (1 << reg);
+ prev_reg = reg;
+ if (skip_past_char(str_p, '-') != FAIL)
+ in_range = 1;
+ else if (skip_past_comma(str_p) == FAIL)
+ first_error (_("bad register list"));
+ }
+ else
+ {
+ int i;
+ if (reg <= prev_reg)
+ first_error (_("bad range in register list"));
+ for (i = prev_reg + 1; i <= reg; i++)
+ {
+ if (core_regs & (1 << i))
+ as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
+ i);
+ else
+ core_regs |= 1 << i;
+ }
+ in_range = 0;
+ }
+ }
+ if (core_regs)
+ {
+ /* Higher register numbers go in higher memory addresses. When splitting a list,
+ right-most sublist should therefore be .saved first. Use recursion for this. */
+ parse_dot_save (str_p, reg);
+ /* We're back from recursion, so emit .save insn for sublist. */
+ s_arm_unwind_save_core (core_regs);
+ return;
+ }
+ /* Handle pseudo-regs, under assumption these are emitted singly. */
+ else if ((reg = arm_reg_parse (str_p, REG_TYPE_PSEUDO)) != FAIL)
+ {
+ /* recurse for remainder of input. Note: No assumption is made regarding which
+ register in core register set holds pseudo-register. It's not considered in
+ ordering check beyond ensuring it's not sandwiched between 2 consecutive
+ registers. */
+ parse_dot_save (str_p, prev_reg + 1);
+ s_arm_unwind_save_pseudo (reg);
+ return;
+ }
+ else
+ as_bad (BAD_SYNTAX);
+}
/* Parse a directive saving FPA registers. */
ignore_rest_of_line ();
}
-/* Convert range and mask_range into a sequence of s_arm_unwind_core
- and s_arm_unwind_pseudo operations. We assume that mask_range will
- not have consecutive bits set, or that one operation per bit is
- acceptable. */
-
-static void
-s_arm_unwind_save_mixed (long range, long mask_range)
-{
- while (mask_range)
- {
- long mask_bit = mask_range & -mask_range;
- long subrange = range & (mask_bit - 1);
-
- if (subrange)
- s_arm_unwind_save_core (subrange);
-
- s_arm_unwind_save_pseudo (mask_bit);
- range &= ~subrange;
- mask_range &= ~mask_bit;
- }
-
- if (range)
- s_arm_unwind_save_core (range);
-}
-
/* Parse an unwind_save directive.
If the argument is non-zero, this is a .vsave directive. */
static void
s_arm_unwind_save (int arch_v6)
{
- char *peek, *mask_peek;
- long range, mask_range;
+ char *peek;
struct reg_entry *reg;
bool had_brace = false;
as_bad (MISSING_FNSTART);
/* Figure out what sort of save we have. */
- peek = mask_peek = input_line_pointer;
+ peek = input_line_pointer;
if (*peek == '{')
{
case REG_TYPE_PSEUDO:
case REG_TYPE_RN:
- mask_range = parse_reg_list (&mask_peek, REGLIST_PSEUDO);
- range = parse_reg_list (&input_line_pointer, REGLIST_RN);
-
- if (range == FAIL || mask_range == FAIL)
- {
- as_bad (_("expected register list"));
- ignore_rest_of_line ();
- return;
- }
-
- demand_empty_rest_of_line ();
-
- s_arm_unwind_save_mixed (range, mask_range);
- return;
+ {
+ if (had_brace)
+ input_line_pointer++;
+ parse_dot_save (&input_line_pointer, -1);
+ demand_empty_rest_of_line ();
+ return;
+ }
case REG_TYPE_VFD:
if (arch_v6)
/* XScale accumulator registers. */
REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
- /* DWARF ABI defines RA_AUTH_CODE to 143. It also reserves 134-142 for future
- expansion. RA_AUTH_CODE here is given the value 143 % 134 to make it easy
- for tc_arm_regname_to_dw2regnum to translate to DWARF reg number using
- 134 + reg_number should the range 134 to 142 be used for more pseudo regs
- in the future. This also helps fit RA_AUTH_CODE into a bitmask. */
- REGDEF(ra_auth_code,12,PSEUDO),
+ /* DWARF ABI defines RA_AUTH_CODE to 143. */
+ REGDEF(ra_auth_code,143,PSEUDO),
};
#undef REGDEF
#undef REGNUM
return 0;
}
-
/* Initialize the DWARF-2 unwind information for this procedure. */
void
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