Set more ports explicitly

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index ae8cd64da50e3e9d2c993c3db81def3a464455c1..e0c7823ededbd797bf060138c1f21684271e8328 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -44,6 +44,8 @@ static Cell* addDsp(Module *module) {
        cell->setParam("\\OPMODEREG", 0);
        cell->setParam("\\PREG", 0);
        cell->setParam("\\USE_MULT", Const("NONE"));
+       cell->setParam("\\USE_SIMD", Const("ONE48"));
+       cell->setParam("\\USE_DPORT", Const("FALSE"));
 
        cell->setPort("\\D", Const(0, 24));
        cell->setPort("\\INMODE", Const(0, 5));

diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v
index cc37f00857af07ff0a935d708d2ffc28b97e3027..8901b215bd8f41f798430a8d59341eeb6e2b4ed5 100644 (file)
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
                .OPMODEREG(0),
                .PREG(0),
                .USE_MULT("MULTIPLY"),
-               .USE_SIMD("ONE48")
+               .USE_SIMD("ONE48"),
+               .USE_DPORT("FALSE")
        ) _TECHMAP_REPLACE_ (
                //Data path
                .A({{5{A[24]}}, A}),