;; condmove conditional moves
;; xfer transfer to/from coprocessor
;; hilo transfer of hi/lo registers
-;; arith integer arithmetic instruction
-;; darith double precision integer arithmetic instructions
+;; arith integer arithmetic and logical instructions
+;; shift integer shift instructions
+;; clz the clz and clo instructions
+;; slt set less than instructions
;; const load constant
;; imul integer multiply
;; imadd integer multiply-add
;; multi multiword sequence (or user asm statements)
;; nop no operation
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,shift,slt,clz,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")]
(const_string "unknown")))
? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
: "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
move\t%L0,%L1\;move\t%M0,%M1
subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "12,8,16")])
"@
daddu\t%0,%z1,%2
daddiu\t%0,%z1,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
;; For the mips16, we need to recognize stack pointer additions
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT"
"dsubu\t%0,%1,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_insn "subsi3_internal_2"
(clz:SI (match_operand:SI 1 "register_operand" "d")))]
"ISA_HAS_CLZ_CLO"
"clz\t%0,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "clz")
(set_attr "mode" "SI")])
(define_insn "clzdi2"
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
"ISA_HAS_DCLZ_DCLO"
"dclz\t%0,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "clz")
(set_attr "mode" "DI")])
\f
;;
(clobber (match_operand:SI 2 "register_operand" "=d"))]
"! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
"subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
else
return "nor\t%0,%.,%1";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
\f
;;
"@
and\t%0,%1,%2
andi\t%0,%1,%x2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16"
"and\t%0,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_expand "iorsi3"
"@
or\t%0,%1,%2
ori\t%0,%1,%x2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16"
"or\t%0,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_expand "xorsi3"
"@
xor\t%0,%1,%2
xori\t%0,%1,%x2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
(define_insn ""
(not:DI (match_operand:DI 2 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"nor\t%0,%z1,%z2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "DI")])
\f
;;
"@
sll\t%0,%1,0
sw\t%1,%0"
- [(set_attr "type" "darith,store")
+ [(set_attr "type" "shift,store")
(set_attr "mode" "SI")
(set_attr "extended_mips16" "yes,*")])
"@
sll\t%0,%1,0
sh\t%1,%0"
- [(set_attr "type" "darith,store")
+ [(set_attr "type" "shift,store")
(set_attr "mode" "SI")
(set_attr "extended_mips16" "yes,*")])
"@
sll\t%0,%1,0
sb\t%1,%0"
- [(set_attr "type" "darith,store")
+ [(set_attr "type" "shift,store")
(set_attr "mode" "SI")
(set_attr "extended_mips16" "yes,*")])
(match_operand:DI 2 "small_int" "I"))))]
"TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
"dsra\t%0,%1,%2"
- [(set_attr "type" "darith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(define_insn ""
(const_int 32))))]
"TARGET_64BIT && !TARGET_MIPS16"
"dsra\t%0,%1,32"
- [(set_attr "type" "darith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xffff"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "darith")
+ [(set_attr "type" "arith")
(set_attr "mode" "HI")])
\f
;;
(set (match_dup 0)
(lshiftrt:DI (match_dup 0) (const_int 32)))]
"operands[1] = gen_lowpart (DImode, operands[1]);"
- [(set_attr "type" "arith")
- (set_attr "mode" "DI")])
+ [(set_attr "type" "multi")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8")])
(define_insn "*zero_extendsidi2_mem"
[(set (match_operand:DI 0 "register_operand" "=d")
"@
sll\t%0,%1,0
lw\t%0,%1"
- [(set_attr "type" "arith,load")
+ [(set_attr "type" "shift,load")
(set_attr "mode" "DI")
(set_attr "extended_mips16" "yes,*")])
return "sll\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(define_insn "ashlsi3_internal1_extend"
return "sll\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")])
return "sll\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
%~2:\;\
sll\t%L0,%L1,%2\n\
%~3:"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "48")])
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sll\t%M0,%L1,%2\;move\t%L0,%.";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
return "dsll\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")])
(define_insn ""
return "dsll\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
return "sra\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(define_insn "ashrsi3_internal2"
return "sra\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
%~2:\;\
sra\t%M0,%M1,%2\n\
%~3:"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "48")])
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
return "dsra\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")])
(define_insn ""
return "dsra\t%0,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
return "srl\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(define_insn "lshrsi3_internal2"
return "srl\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
%~2:\;\
srl\t%M0,%M1,%2\n\
%~3:"
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "48")])
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%L0,%M1,%2\;move\t%M0,%.";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
}
- [(set_attr "type" "darith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "16")])
return "dsrl\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")])
(define_insn ""
return "dsrl\t%0,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
return "ror\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "SI")])
(define_insn "rotrdi3"
return "dror\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "shift")
(set_attr "mode" "DI")])
(const_int 0)))]
"!TARGET_MIPS16"
"sltu\t%0,%1,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
(const_int 0)))]
"TARGET_MIPS16"
"sltu\t%1,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "seq_di_zero"
(const_int 0)))]
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%1,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
(const_int 0)))]
"TARGET_64BIT && TARGET_MIPS16"
"sltu\t%1,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn "seq_si"
"@
xor\t%0,%1,%2\;sltu\t%0,%0,1
xori\t%0,%1,%2\;sltu\t%0,%0,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
"@
xor\t%0,%1,%2\;sltu\t%0,%0,1
xori\t%0,%1,%2\;sltu\t%0,%0,1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(const_int 0)))]
"!TARGET_MIPS16"
"sltu\t%0,%.,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "sne_di_zero"
(const_int 0)))]
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%.,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn "sne_si"
"@
xor\t%0,%1,%2\;sltu\t%0,%.,%0
xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
"@
xor\t%0,%1,%2\;sltu\t%0,%.,%0
xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16"
"slt\t%0,%z2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:SI 2 "register_operand" "d")))]
"TARGET_MIPS16"
"slt\t%2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "sgt_di"
(match_operand:DI 2 "reg_or_0_operand" "dJ")))]
"TARGET_64BIT && !TARGET_MIPS16"
"slt\t%0,%z2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16"
"slt\t%2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_expand "sge"
(match_operand:SI 2 "arith_operand" "dI")))]
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
(match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(match_operand:SI 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
"slt\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
"slt\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
(match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && !TARGET_MIPS16"
"slt\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "arith_operand" "d,I")))]
"TARGET_64BIT && TARGET_MIPS16"
"slt\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "slt\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "slt\t%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
(const_int 4)
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "slt\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "slt\t%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
(const_int 4)
(match_operand:SI 2 "register_operand" "d")))]
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16"
"sltu\t%0,%z2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:SI 2 "register_operand" "d")))]
"TARGET_MIPS16"
"sltu\t%2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn "sgtu_di"
(match_operand:DI 2 "reg_or_0_operand" "dJ")))]
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%z2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_MIPS16"
"sltu\t%2,%1"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_expand "sgeu"
(match_operand:SI 2 "arith_operand" "dI")))]
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
(match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
(match_operand:SI 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
"sltu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
(match_operand:SI 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
"sltu\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
(match_operand:DI 2 "arith_operand" "dI")))]
"TARGET_64BIT && !TARGET_MIPS16"
"sltu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
(match_operand:DI 2 "arith_operand" "d,I")))]
"TARGET_64BIT && TARGET_MIPS16"
"sltu\t%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")])
(define_insn ""
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "sltu\t%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "SI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
(const_int 4)
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
return "sltu\t%0,%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")])
(define_insn ""
operands[2] = GEN_INT (INTVAL (operands[2])+1);
return "sltu\t%1,%2";
}
- [(set_attr "type" "arith")
+ [(set_attr "type" "slt")
(set_attr "mode" "DI")
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
(const_int 4)
(match_operand:SI 2 "register_operand" "d")))]
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "SI")
(set_attr "length" "8")])
(match_operand:DI 2 "register_operand" "d")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
"sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "arith")
+ [(set_attr "type" "multi")
(set_attr "mode" "DI")
(set_attr "length" "8")])
else
return "#nop";
}
- [(set_attr "type" "arith")])
+ [(set_attr "type" "nop")])
\f
;; MIPS4 Conditional move instructions.