S_028810_PS_UCP_MODE(3) |
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
- S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+ S_028810_DX_LINEAR_ATTR_CLIP_ENA(1) |
+ S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
rs->multisample_enable = state->multisample;
/* offset */
state->fill_back != PIPE_POLYGON_MODE_FILL) |
S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
- r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
return rs;
}
r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
- r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+ r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
}
/* The cs checker requires this register to be set. */
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+ r600_store_context_reg_seq(cb, R_028350_SX_MISC, 2);
+ r600_store_value(cb, 0);
+ r600_store_value(cb, S_028354_SURFACE_SYNC_MASK(0xf));
return;
}
#define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21)
#define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1)
#define C_028810_VTX_KILL_OR 0xFFDFFFFF
+#define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22)
+#define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1)
+#define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF
#define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24)
#define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1)
#define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF
}
/* SX_MISC */
- if (ctx->b.chip_class <= R700) {
+ if (ctx->b.chip_class == R600) {
num_dw += 3;
}
r600_flush_emit(ctx);
/* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */
- if (ctx->b.chip_class <= R700) {
+ if (ctx->b.chip_class == R600) {
r600_write_context_reg(cs, R_028350_SX_MISC, 0);
}
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
+ if (rctx->b.chip_class == R700) {
+ rs->pa_cl_clip_cntl |=
+ S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
+ }
rs->multisample_enable = state->multisample;
/* offset */
if (rctx->b.chip_class == R700) {
r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
}
- r600_store_context_reg(&rs->buffer, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
+ if (rctx->b.chip_class == R600) {
+ r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
+ S_028350_MULTIPASS(state->rasterizer_discard));
+ }
return rs;
}
r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
+ if (rctx->b.chip_class == R700)
+ r600_store_context_reg(cb, R_028350_SX_MISC, 0);
if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
+
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
#define S_028810_VTX_KILL_OR(x) (((x) & 0x1) << 21)
#define G_028810_VTX_KILL_OR(x) (((x) >> 21) & 0x1)
#define C_028810_VTX_KILL_OR 0xFFDFFFFF
+#define S_028810_DX_RASTERIZATION_KILL(x) (((x) & 0x1) << 22) /* R700 only? */
+#define G_028810_DX_RASTERIZATION_KILL(x) (((x) >> 22) & 0x1)
+#define C_028810_DX_RASTERIZATION_KILL 0xFFBFFFFF
#define S_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x1) << 24)
#define G_028810_DX_LINEAR_ATTR_CLIP_ENA(x) (((x) >> 24) & 0x1)
#define C_028810_DX_LINEAR_ATTR_CLIP_ENA 0xFEFFFFFF