Updated PGEN model to have level triggered reset (matches actual hardware behavior

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 5d9d677503f4682d3eab828e6eed44bd718dd9eb..6fba941a013a19b761252db15ae45608eefaef90 100644 (file)
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
        localparam COUNT_MAX =  PATTERN_LEN - 1'h1;
 
        reg[3:0] count = 0;
-       always @(posedge CLK) begin
-               if(!nRST) begin
-                       count   <= COUNT_MAX;
-               end
+       always @(posedge CLK, negedge nRST) begin
+
+               if(!nRST)
+                       count   <= 0;
 
                else begin
                        count   <= count - 1'h1;