---------- Begin Simulation Statistics ----------
-host_inst_rate 130186 # Simulator instruction rate (inst/s)
-host_mem_usage 285488 # Number of bytes of host memory used
-host_seconds 11733.03 # Real time elapsed on the host
-host_tick_rate 52071207 # Simulator tick rate (ticks/s)
+host_inst_rate 189714 # Simulator instruction rate (inst/s)
+host_mem_usage 264736 # Number of bytes of host memory used
+host_seconds 8051.48 # Real time elapsed on the host
+host_tick_rate 75880827 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1527476062 # Number of instructions simulated
sim_seconds 0.610953 # Number of seconds simulated
system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 164362000 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 2150205320 # num instructions consuming a value
+system.cpu.iew.WB:consumers 2150204737 # num instructions consuming a value
system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1432458045 # num instructions producing a value
+system.cpu.iew.WB:producers 1432457554 # num instructions producing a value
system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle
system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 6555 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispNonSpecInsts 9848 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 24902522 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 24902521 # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 446588315 23.46% 91.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 446588314 23.46% 91.14% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 1903752721 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 1903752720 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 147240855 12.30% 86.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 95168176 7.95% 94.45% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 147240856 12.30% 86.50% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 95168175 7.95% 94.45% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle
system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 1913488178 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 5017400189 # Number of integer instruction queue reads
+system.cpu.iq.int_alu_accesses 1913488177 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 5017400187 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses
system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 2368910398 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1903752721 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 6555 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsAdded 2368907105 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 1903752720 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 6002 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1472792375 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 9295 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1472780543 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency
system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 404346 # number of writebacks
-system.cpu.memDep0.conflictingLoads 432040536 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 167867809 # Number of conflicting stores.
+system.cpu.memDep0.conflictingLoads 432038121 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 167866970 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit.
system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads
projects / gem5.git / commitdiff