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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index f5a2175ce22c16386e58b6a4eea1bbc86d84299f..6e2470a0dfd4d94775497f6045961d3ec5c821f2 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -119,9 +119,9 @@ in the decoder is greatly increased.
 
 # Single Predication
 
-This is a standard mode normally found in Vector ISAs.  every element in rvery source Vector and in the destination uses the same bit of one single predicate mask.
+This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.
 
-Note however that in SVSTATE, implementors MUST increment both srcstep and dststep, and that the two must be equal at all times.
+In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times.
 
 # Twin Predication