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stats: Update the solaris boot stats for the new op classes.
authorGabe Black <gabeblack@google.com>
Tue, 4 Apr 2017 10:11:17 +0000 (03:11 -0700)
committerGabe Black <gabeblack@google.com>
Wed, 5 Apr 2017 18:37:29 +0000 (18:37 +0000)
The change below introduced some new op classes which have their own stats,
and the counts the instructions used to be under have gone down.

    commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318
    Author: Fernando Endo <fernando.endo2@gmail.com>
    Date:   Sat Oct 15 14:58:45 2016 -0500

        cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass

Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb
Reviewed-on: https://gem5-review.googlesource.com/2648
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout patch | blob | history
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt patch | blob | history

diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index e473f5b49ccc2b74ba592f631691a0199129af3d..ed41ed4a0c3c5432a01c7e9d5403c8caba64b25c 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -28,7 +28,7 @@ kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=atomic
-mem_ranges=1048576:68157439 2147483648:2415919103
+mem_ranges=1048576:68157439:0:0:0:0 2147483648:2415919103:0:0:0:0
 memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
 mmap_using_noreserve=false
 multi_thread=false
@@ -71,7 +71,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
+ranges=133412421632:133412421639:0:0:0:0 134217728000:554050781183:0:0:0:0 644245094400:652835028991:0:0:0:0 725849473024:1095485095935:0:0:0:0 1099255955456:1099255955463:0:0:0:0
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
@@ -204,6 +204,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -211,7 +212,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=133446500352:133446508543
+range=133446500352:133446508543:0:0:0:0
 port=system.membus.master[5]
 
 [system.intrctrl]
@@ -297,6 +298,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -304,7 +306,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=133429198848:133429207039
+range=133429198848:133429207039:0:0:0:0
 port=system.membus.master[4]
 
 [system.partition_desc]
@@ -315,6 +317,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -322,7 +325,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=133445976064:133445984255
+range=133445976064:133445984255:0:0:0:0
 port=system.membus.master[6]
 
 [system.physmem0]
@@ -333,6 +336,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -340,7 +344,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=1048576:68157439
+range=1048576:68157439:0:0:0:0
 port=system.membus.master[7]
 
 [system.physmem1]
@@ -351,6 +355,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -358,7 +363,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=2147483648:2415919103
+range=2147483648:2415919103:0:0:0:0
 port=system.membus.master[8]
 
 [system.rom]
@@ -369,6 +374,7 @@ conf_table_reported=true
 default_p_state=UNDEFINED
 eventq_index=0
 in_addr_map=true
+kvm_map=true
 latency=60
 latency_var=0
 null=false
@@ -376,7 +382,7 @@ p_state_clk_gate_bins=20
 p_state_clk_gate_max=2000000000
 p_state_clk_gate_min=2
 power_model=Null
-range=1099243192320:1099251580927
+range=1099243192320:1099251580927:0:0:0:0
 port=system.membus.master[3]
 
 [system.t1000]
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
index 940cdb03cd5ac863cd0df5bac2f5ea8bc8a5077f..913ebaa55e9da54b484e3d0c2cfbaa0d41ab7688 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -6,13 +6,14 @@
         "mmap_using_noreserve": false, 
         "kernel_addr_check": true, 
         "rom": {
-            "range": "1099243192320:1099251580927", 
+            "range": "1099243192320:1099251580927:0:0:0:0", 
             "latency": 60, 
             "name": "rom", 
             "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
             "p_state_clk_gate_bins": 20, 
             "default_p_state": "UNDEFINED", 
+            "kvm_map": true, 
             "clk_domain": "system.clk_domain", 
             "power_model": null, 
             "latency_var": 0, 
@@ -31,11 +32,11 @@
         }, 
         "bridge": {
             "ranges": [
-                "133412421632:133412421639", 
-                "134217728000:554050781183", 
-                "644245094400:652835028991", 
-                "725849473024:1095485095935", 
-                "1099255955456:1099255955463"
+                "133412421632:133412421639:0:0:0:0", 
+                "134217728000:554050781183:0:0:0:0", 
+                "644245094400:652835028991:0:0:0:0", 
+                "725849473024:1095485095935:0:0:0:0", 
+                "1099255955456:1099255955463:0:0:0:0"
             ], 
             "slave": {
                 "peer": "system.membus.master[2]", 
@@ -574,8 +575,8 @@
         "thermal_model": null, 
         "hypervisor_addr": 1099243257856, 
         "mem_ranges": [
-            "1048576:68157439", 
-            "2147483648:2415919103"
+            "1048576:68157439:0:0:0:0", 
+            "2147483648:2415919103:0:0:0:0"
         ], 
         "cxx_class": "SparcSystem", 
         "work_begin_cpu_id_exit": -1, 
@@ -596,13 +597,14 @@
         ], 
         "work_begin_ckpt_count": 0, 
         "partition_desc": {
-            "range": "133445976064:133445984255", 
+            "range": "133445976064:133445984255:0:0:0:0", 
             "latency": 60, 
             "name": "partition_desc", 
             "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
             "p_state_clk_gate_bins": 20, 
             "default_p_state": "UNDEFINED", 
+            "kvm_map": true, 
             "clk_domain": "system.clk_domain", 
             "power_model": null, 
             "latency_var": 0, 
@@ -633,13 +635,14 @@
             "domain_id": -1
         }, 
         "hypervisor_desc": {
-            "range": "133446500352:133446508543", 
+            "range": "133446500352:133446508543:0:0:0:0", 
             "latency": 60, 
             "name": "hypervisor_desc", 
             "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
             "p_state_clk_gate_bins": 20, 
             "default_p_state": "UNDEFINED", 
+            "kvm_map": true, 
             "clk_domain": "system.clk_domain", 
             "power_model": null, 
             "latency_var": 0, 
@@ -743,13 +746,14 @@
             "use_default_range": false
         }, 
         "nvram": {
-            "range": "133429198848:133429207039", 
+            "range": "133429198848:133429207039:0:0:0:0", 
             "latency": 60, 
             "name": "nvram", 
             "p_state_clk_gate_min": 2, 
             "eventq_index": 0, 
             "p_state_clk_gate_bins": 20, 
             "default_p_state": "UNDEFINED", 
+            "kvm_map": true, 
             "clk_domain": "system.clk_domain", 
             "power_model": null, 
             "latency_var": 0, 
@@ -801,13 +805,14 @@
         }, 
         "physmem": [
             {
-                "range": "1048576:68157439", 
+                "range": "1048576:68157439:0:0:0:0", 
                 "latency": 60, 
                 "name": "physmem0", 
                 "p_state_clk_gate_min": 2, 
                 "eventq_index": 0, 
                 "p_state_clk_gate_bins": 20, 
                 "default_p_state": "UNDEFINED", 
+                "kvm_map": true, 
                 "clk_domain": "system.clk_domain", 
                 "power_model": null, 
                 "latency_var": 0, 
@@ -825,13 +830,14 @@
                 "in_addr_map": true
             }, 
             {
-                "range": "2147483648:2415919103", 
+                "range": "2147483648:2415919103:0:0:0:0", 
                 "latency": 60, 
                 "name": "physmem1", 
                 "p_state_clk_gate_min": 2, 
                 "eventq_index": 0, 
                 "p_state_clk_gate_bins": 20, 
                 "default_p_state": "UNDEFINED", 
+                "kvm_map": true, 
                 "clk_domain": "system.clk_domain", 
                 "power_model": null, 
                 "latency_var": 0, 
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index 8347db8a74dbffeb1c09b3627e7125461c5533c5..84db9abea2706038e3d6b2d611ab8a58226e6970 100755 (executable)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solari
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  4 2017 02:30:37
-gem5 started Apr  4 2017 02:30:47
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 2108
+gem5 compiled Apr  4 2017 02:52:44
+gem5 started Apr  4 2017 02:52:54
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 16631
 command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 
 Global frequency set at 2000000000 ticks per second
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index e3f3402793623a38c1b2bab348f420bce502b615..65da9a2c0fd642d7a7dc648cca79e714efa915cf 100644 (file)
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.233778                       # Nu
 sim_ticks                                  4467555024                       # Number of ticks simulated
 final_tick                                 4467555024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                2932422                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2933575                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                5879301                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 552092                       # Number of bytes of host memory used
-host_seconds                                   759.88                       # Real time elapsed on the host
+host_inst_rate                                2912008                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2913153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                5838373                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 551728                       # Number of bytes of host memory used
+host_seconds                                   765.21                       # Real time elapsed on the host
 sim_insts                                  2228284650                       # Number of instructions simulated
 sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -150,7 +150,9 @@ system.cpu.op_class::FloatAdd                 8419779      0.38%     75.09% # Cl
 system.cpu.op_class::FloatCmp                       0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::FloatCvt                       0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::FloatMult                      0      0.00%     75.09% # Class of executed instruction
+system.cpu.op_class::FloatMultAcc                   0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::FloatDiv                       0      0.00%     75.09% # Class of executed instruction
+system.cpu.op_class::FloatMisc                      0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::FloatSqrt                      0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::SimdAdd                        0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::SimdAddAcc                     0      0.00%     75.09% # Class of executed instruction
@@ -172,8 +174,10 @@ system.cpu.op_class::SimdFloatMisc                  0      0.00%     75.09% # Cl
 system.cpu.op_class::SimdFloatMult                  0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::SimdFloatMultAcc               0      0.00%     75.09% # Class of executed instruction
 system.cpu.op_class::SimdFloatSqrt                  0      0.00%     75.09% # Class of executed instruction
-system.cpu.op_class::MemRead                356274529     15.95%     91.04% # Class of executed instruction
-system.cpu.op_class::MemWrite               200199782      8.96%    100.00% # Class of executed instruction
+system.cpu.op_class::MemRead                352214742     15.77%     90.86% # Class of executed instruction
+system.cpu.op_class::MemWrite               198071026      8.87%     99.72% # Class of executed instruction
+system.cpu.op_class::FloatMemRead             4059787      0.18%     99.90% # Class of executed instruction
+system.cpu.op_class::FloatMemWrite            2128756      0.10%    100.00% # Class of executed instruction
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                 2233583679                       # Class of executed instruction