build/sim: add Verilator FST tracing support.

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 28b45058fd852558877aaa9a40ff961fc8f3535f..422baacdda457c4d72f8651b5ef8728670a1bc5e 100644 (file)
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -7,7 +7,7 @@ ifeq ($(UNAME_S),Darwin)
        LDFLAGS += -lpthread -ljson-c -lm -lstdc++ -ldl -levent
 else
        CC ?= gcc
-       CFLAGS += -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
+       CFLAGS += -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE) $(if $(TRACE_FST), -DTRACE_FST)
        LDFLAGS += -lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent
 endif
 
@@ -42,6 +42,7 @@ sim: mkdir $(OBJS_SIM)
                -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
                -LDFLAGS "$(LDFLAGS)" \
                --trace \
+               $(if $(TRACE_FST), --trace-fst,) \
                $(if $(COVERAGE), --coverage,) \
                --unroll-count 256 \
                $(INC_DIR) \

diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index 931b409952160ce963d4be1fdfa34ae6bac3d596..0f74c340fa19e5e0b30e4bbf23b6a73103c81045 100644 (file)
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -4,12 +4,18 @@
 #include <stdlib.h>
 #include <string.h>
 #include "Vdut.h"
-#include "Vdut.h"
 #include "verilated.h"
+#ifdef TRACE_FST
+#include "verilated_fst_c.h"
+#else
 #include "verilated_vcd_c.h"
-#include <verilated.h>
+#endif
 
+#ifdef TRACE_FST
+VerilatedFstC* tfp;
+#else
 VerilatedVcdC* tfp;
+#endif
 long tfp_start;
 long tfp_end;
 
@@ -30,9 +36,15 @@ extern "C" void litex_sim_init_tracer(void *vdut, long start, long end)
   tfp_start = start;
   tfp_end = end;
   Verilated::traceEverOn(true);
-  tfp = new VerilatedVcdC;
-  dut->trace(tfp, 99);
-  tfp->open("dut.vcd");
+#ifdef TRACE_FST
+      tfp = new VerilatedFstC;
+      dut->trace(tfp, 99);
+      tfp->open("dut.fst");
+#else
+      tfp = new VerilatedVcdC;
+      dut->trace(tfp, 99);
+      tfp->open("dut.vcd");
+#endif
 }
 
 extern "C" void litex_sim_tracer_dump()

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 530d6a668d6ea968f1823940542f7eb475bca2e9..5270e3301741655059e7003bbb0ad5083a620eb1 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -88,7 +88,7 @@ extern "C" void litex_sim_init(void **out)
 
     dut = new Vdut;
 
-    litex_sim_init_tracer(dut, {},{});
+    litex_sim_init_tracer(dut, {}, {});
 
 """.format(trace_start, trace_end)
     for args in platform.sim_requested:
@@ -117,20 +117,21 @@ def _generate_sim_config(config):
     tools.write_to_file("sim_config.js", content)
 
 
-def _build_sim(build_name, sources, threads, coverage, opt_level="O3"):
+def _build_sim(build_name, sources, threads, coverage, opt_level="O3", trace_fst=False):
     makefile = os.path.join(core_directory, 'Makefile')
     cc_srcs = []
     for filename, language, library in sources:
         cc_srcs.append("--cc " + filename + " ")
     build_script_contents = """\
 rm -rf obj_dir/
-make -C . -f {} {} {} {} {}
+make -C . -f {} {} {} {} {} {}
 mkdir -p modules && cp obj_dir/*.so modules
 """.format(makefile,
     "CC_SRCS=\"{}\"".format("".join(cc_srcs)),
     "THREADS={}".format(threads) if int(threads) > 1 else "",
     "COVERAGE=1" if coverage else "",
     "OPT_LEVEL={}".format(opt_level),
+    "TRACE_FST=1" if trace_fst else "",
     )
     build_script_file = "build_" + build_name + ".sh"
     tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
@@ -171,7 +172,7 @@ class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
             toolchain_path=None, serial="console", build=True, run=True, threads=1,
             verbose=True, sim_config=None, coverage=False, opt_level="O0",
-            trace=False, trace_start=0, trace_end=-1):
+            trace=False, trace_fst=False, trace_start=0, trace_end=-1):
 
         # create build directory
         os.makedirs(build_dir, exist_ok=True)
@@ -201,7 +202,7 @@ class SimVerilatorToolchain:
                 _generate_sim_config(sim_config)
 
             # build
-            _build_sim(build_name, platform.sources, threads, coverage, opt_level)
+            _build_sim(build_name, platform.sources, threads, coverage, opt_level, trace_fst)
 
         # run
         if run:

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 272286f9229ee9f934825de65a40fef28cebf21e..8dd472c48c72520c50c34fc365f2319c1f7cb512 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -266,9 +266,10 @@ def main():
     parser.add_argument("--local-ip",             default="192.168.1.50",  help="Local IP address of SoC (default=192.168.1.50)")
     parser.add_argument("--remote-ip",            default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
     parser.add_argument("--with-analyzer",        action="store_true",     help="Enable Analyzer support")
-    parser.add_argument("--trace",                action="store_true",     help="Enable VCD tracing")
-    parser.add_argument("--trace-start",          default=0,               help="Cycle to start VCD tracing")
-    parser.add_argument("--trace-end",            default=-1,              help="Cycle to end VCD tracing")
+    parser.add_argument("--trace",                action="store_true",     help="Enable Tracing")
+    parser.add_argument("--trace-fst",            action="store_true",     help="Enable FST tracing (default=VCD)")
+    parser.add_argument("--trace-start",          default=0,               help="Cycle to start tracing")
+    parser.add_argument("--trace-end",            default=-1,              help="Cycle to end tracing")
     parser.add_argument("--opt-level",            default="O3",            help="Compilation optimization level")
     args = parser.parse_args()
 
@@ -321,13 +322,17 @@ def main():
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
     vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
-        opt_level=args.opt_level,
-        trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
+        opt_level   = args.opt_level,
+        trace       = args.trace,
+        trace_fst   = args.trace_fst,
+        trace_start = int(args.trace_start),
+        trace_end   = int(args.trace_end))
     if args.with_analyzer:
         soc.analyzer.export_csv(vns, "analyzer.csv")
     builder.build(build=False, threads=args.threads, sim_config=sim_config,
         opt_level   = args.opt_level,
         trace       = args.trace,
+        trace_fst   = args.trace,
         trace_start = int(args.trace_start),
         trace_end   = int(args.trace_end)
     )