Fix some missing and extra includes around the codebase.
Change-Id: Ibf314b43a966943a8096958f68382e1e245f29e3
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38738
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
#ifndef __ARCH_GENERIC_INTERRUPTS_HH__
#define __ARCH_GENERIC_INTERRUPTS_HH__
+#include "base/logging.hh"
#include "params/BaseInterrupts.hh"
#include "sim/sim_object.hh"
#include <fstream>
#include <iostream>
#include <sstream>
-#include <string>
#include "base/atomicio.hh"
-#include "base/debug.hh"
#include "base/logging.hh"
#include "base/output.hh"
#include "base/str.hh"
#ifndef __BASE_TRACE_HH__
#define __BASE_TRACE_HH__
+#include <ostream>
#include <string>
#include <sstream>
#include <iostream>
#include <queue>
#include <sstream>
+#include <string>
#include "base/logging.hh"
+#include "base/types.hh"
#include "cpu/activity.hh"
#include "cpu/minor/trace.hh"
#include "cpu/timebuf.hh"
#include "cpu/minor/decode.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "cpu/minor/pipeline.hh"
#include "debug/Decode.hh"
#ifndef __CPU_MINOR_DECODE_HH__
#define __CPU_MINOR_DECODE_HH__
+#include <vector>
+
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/dyn_inst.hh"
#include <iostream>
#include "base/refcnt.hh"
-#include "cpu/minor/buffers.hh"
+#include "base/types.hh"
#include "cpu/inst_seq.hh"
+#include "cpu/minor/buffers.hh"
#include "cpu/static_inst.hh"
#include "cpu/timing_expr.hh"
#include "sim/faults.hh"
+#include "sim/insttracer.hh"
namespace Minor
{
#ifndef __CPU_MINOR_EXECUTE_HH__
#define __CPU_MINOR_EXECUTE_HH__
+#include <vector>
+
+#include "base/types.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/func_unit.hh"
#include <sstream>
#include "base/cast.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "cpu/minor/pipeline.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
#ifndef __CPU_MINOR_FETCH1_HH__
#define __CPU_MINOR_FETCH1_HH__
+#include <vector>
+
+#include "cpu/base.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
-#include "cpu/base.hh"
#include "mem/packet.hh"
namespace Minor
#include "arch/decoder.hh"
#include "arch/utility.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "cpu/minor/pipeline.hh"
#include "cpu/pred/bpred_unit.hh"
#include "debug/Branch.hh"
#ifndef __CPU_MINOR_FETCH2_HH__
#define __CPU_MINOR_FETCH2_HH__
+#include <vector>
+
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include <sstream>
#include <typeinfo>
+#include "base/trace.hh"
#include "debug/MinorTiming.hh"
#include "enums/OpClass.hh"
#ifndef __CPU_MINOR_FUNC_UNIT_HH__
#define __CPU_MINOR_FUNC_UNIT_HH__
+#include <cstdint>
+#include <ostream>
+#include <string>
+#include <vector>
+
+#include "base/types.hh"
+#include "cpu/func_unit.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/dyn_inst.hh"
-#include "cpu/func_unit.hh"
#include "cpu/timing_expr.hh"
#include "params/MinorFU.hh"
#include "params/MinorFUPool.hh"
#include "params/MinorOpClass.hh"
#include "params/MinorOpClassSet.hh"
#include "sim/clocked_object.hh"
+#include "sim/sim_object.hh"
/** Boxing for MinorOpClass to get around a build problem with C++11 but
* also allow for future additions to op class checking */
#include "arch/locked_mem.hh"
#include "base/logging.hh"
-#include "cpu/minor/cpu.hh"
+#include "base/trace.hh"
#include "cpu/minor/exec_context.hh"
#include "cpu/minor/execute.hh"
#include "cpu/minor/pipeline.hh"
#ifndef __CPU_MINOR_NEW_LSQ_HH__
#define __CPU_MINOR_NEW_LSQ_HH__
+#include <string>
+#include <vector>
+
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/minor/trace.hh"
+#include "mem/packet.hh"
namespace Minor
{
#ifndef __CPU_MINOR_SCOREBOARD_HH__
#define __CPU_MINOR_SCOREBOARD_HH__
+#include <vector>
+
+#include "base/types.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/dyn_inst.hh"
#include "cpu/minor/trace.hh"
#include <iostream>
#include <queue>
-#include <vector>
#include "base/logging.hh"
#include "base/trace.hh"
#ifndef __CPU_O3_LSQ_HH__
#define __CPU_O3_LSQ_HH__
+#include <cassert>
+#include <cstdint>
+#include <list>
#include <map>
#include <queue>
+#include <vector>
#include "arch/generic/tlb.hh"
+#include "base/flags.hh"
+#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/lsq_unit.hh"
#include "cpu/utils.hh"
#include "cpu/o3/scoreboard.hh"
-#include "config/the_isa.hh"
-#include "debug/Scoreboard.hh"
-
Scoreboard::Scoreboard(const std::string &_my_name,
unsigned _numPhysicalRegs)
: _name(_my_name),
#ifndef __CPU_O3_SCOREBOARD_HH__
#define __CPU_O3_SCOREBOARD_HH__
-#include <iostream>
-#include <utility>
+#include <cassert>
#include <vector>
+#include "base/compiler.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
-#include "cpu/o3/comm.hh"
+#include "cpu/reg_class.hh"
#include "debug/Scoreboard.hh"
-
/**
* Implements a simple scoreboard to track which registers are
* ready. This class operates on the unified physical register space,
#include <algorithm>
#include "base/logging.hh"
-#include "base/random.hh"
-#include "base/trace.hh"
#include "cpu/testers/traffic_gen/base.hh"
-#include "debug/TrafficGen.hh"
-#include "sim/system.hh"
BaseGen::BaseGen(SimObject &obj, RequestorID requestor_id, Tick _duration)
: _name(obj.name()), requestorId(requestor_id),
#ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__
#define __CPU_TRAFFIC_GEN_BASE_GEN_HH__
+#include <cstdint>
#include <string>
#include "base/types.hh"
#include "mem/packet_access.hh"
#include "params/EnergyCtrl.hh"
#include "sim/dvfs_handler.hh"
+#include "sim/serialize.hh"
EnergyCtrl::EnergyCtrl(const Params &p)
: BasicPioDevice(p, PIO_NUM_FIELDS * 4), // each field is 32 bit
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "cpu/base.hh"
#include "debug/Timer.hh"
#include "dev/arm/base_gic.hh"
#ifndef __DEV_ARM_GENERIC_TIMER_HH__
#define __DEV_ARM_GENERIC_TIMER_HH__
+#include <cstdint>
+#include <vector>
+
#include "arch/arm/isa_device.hh"
#include "arch/arm/system.hh"
+#include "base/addr_range.hh"
+#include "base/bitunion.hh"
+#include "base/types.hh"
#include "dev/arm/base_gic.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"
#include "sim/core.hh"
+#include "sim/drain.hh"
+#include "sim/eventq.hh"
+#include "sim/serialize.hh"
#include "sim/sim_object.hh"
/// @file
#include "dev/arm/gic_v3_its.hh"
+#include <cassert>
+#include <functional>
+
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "debug/AddrRanges.hh"
#include "debug/Drain.hh"
#include "debug/GIC.hh"
#ifndef __DEV_ARM_GICV3_ITS_H__
#define __DEV_ARM_GICV3_ITS_H__
+#include <cstdint>
+#include <memory>
#include <queue>
+#include <vector>
+#include "base/addr_range.hh"
+#include "base/bitunion.hh"
#include "base/coroutine.hh"
+#include "base/types.hh"
#include "dev/dma_device.hh"
#include "params/Gicv3Its.hh"
#include "dev/arm/smmu_v3_proc.hh"
+#include <cassert>
+#include <functional>
+
#include "dev/arm/smmu_v3.hh"
#include "sim/system.hh"
#include "dev/arm/timer_a9global.hh"
+#include <cassert>
+
#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/Checkpoint.hh"
#include "debug/Timer.hh"
#ifndef __DEV_ARM_GLOBAL_TIMER_HH__
#define __DEV_ARM_GLOBAL_TIMER_HH__
+#include <cstdint>
+
+#include "base/types.hh"
#include "base/bitunion.hh"
+#include "base/types.hh"
#include "dev/io_device.hh"
#include "params/A9GlobalTimer.hh"
+#include "sim/eventq.hh"
+#include "sim/serialize.hh"
/** @file
* This implements the Cortex A9-MPCore global timer from TRM rev r4p1.
#include "dev/arm/timer_cpulocal.hh"
+#include <cassert>
+
#include "arch/arm/system.hh"
#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/Checkpoint.hh"
#include "debug/Timer.hh"
#ifndef __DEV_ARM_LOCALTIMER_HH__
#define __DEV_ARM_LOCALTIMER_HH__
+#include <cstdint>
+#include <memory>
+#include <vector>
+
#include "base/bitunion.hh"
+#include "base/types.hh"
#include "dev/io_device.hh"
#include "params/CpuLocalTimer.hh"
+#include "sim/serialize.hh"
/** @file
* This implements the cpu local timer from the Cortex-A9 MPCore
#include "dev/arm/timer_sp804.hh"
+#include <cassert>
+
#include "base/intmath.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/Checkpoint.hh"
#include "debug/Timer.hh"
#ifndef __DEV_ARM_SP804_HH__
#define __DEV_ARM_SP804_HH__
+#include <cstdint>
+
+#include "base/bitunion.hh"
+#include "base/types.hh"
#include "dev/arm/amba_device.hh"
#include "params/Sp804.hh"
+#include "sim/eventq.hh"
+#include "sim/serialize.hh"
/** @file
* This implements the dual Sp804 timer block
#include "dev/hsa/hsa_packet_processor.hh"
+#include <cassert>
#include <cstring>
#include "base/chunk_generator.hh"
#include "base/compiler.hh"
+#include "base/logging.hh"
+#include "base/trace.hh"
#include "debug/HSAPacketProcessor.hh"
#include "dev/dma_device.hh"
#include "dev/hsa/hsa_device.hh"
#ifndef __DEV_HSA_HSA_PACKET_PROCESSOR__
#define __DEV_HSA_HSA_PACKET_PROCESSOR__
+#include <algorithm>
#include <cstdint>
+#include <vector>
-#include <queue>
-
+#include "base/types.hh"
#include "dev/dma_device.hh"
#include "dev/hsa/hsa.h"
#include "dev/hsa/hsa_queue.hh"
#include "params/HSAPacketProcessor.hh"
+#include "sim/eventq.hh"
#define AQL_PACKET_SIZE 64
#define PAGE_SIZE 4096
#include "debug/Checkpoint.hh"
#include "dev/i2c/device.hh"
#include "mem/packet_access.hh"
+#include "sim/serialize.hh"
// clang complains about std::set being overloaded with Packet::set if
// we open up the entire namespace std
#ifndef __DEV_DIST_ETHERLINK_HH__
#define __DEV_DIST_ETHERLINK_HH__
+#include <cassert>
#include <iostream>
+#include "base/types.hh"
#include "dev/net/etherlink.hh"
#include "params/DistEtherLink.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_object.hh"
class DistIface;
class EthPacketData;
#include "dev/net/etherlink.hh"
+#include <cassert>
#include <cmath>
#include <deque>
#include <string>
#include <vector>
+#include "base/logging.hh"
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/Ethernet.hh"
#define __DEV_NET_ETHERLINK_HH__
#include <queue>
+#include <utility>
#include "base/types.hh"
#include "dev/net/etherint.hh"
#include <map>
#include <set>
+#include <string>
+#include <vector>
#include "base/inet.hh"
#include "dev/net/etherint.hh"
#include "dev/net/pktfifo.hh"
#include "params/EtherSwitch.hh"
#include "sim/eventq.hh"
+#include "sim/serialize.hh"
#include "sim/sim_object.hh"
class EtherSwitch : public SimObject
#ifndef __DEV_NET_I8254XGBE_HH__
#define __DEV_NET_I8254XGBE_HH__
+#include <cstdint>
#include <deque>
#include <string>
#include "base/inet.hh"
+#include "base/trace.hh"
+#include "base/types.hh"
#include "debug/EthernetDesc.hh"
#include "debug/EthernetIntr.hh"
#include "dev/net/etherdevice.hh"
#include "dev/pci/device.hh"
#include "params/IGbE.hh"
#include "sim/eventq.hh"
+#include "sim/serialize.hh"
class IGbEInt;
#include "debug/PS2.hh"
#include "dev/ps2/types.hh"
#include "params/PS2Device.hh"
+#include "sim/serialize.hh"
PS2Device::PS2Device(const PS2DeviceParams &p)
: SimObject(p)
#include "debug/PS2.hh"
#include "dev/ps2/types.hh"
#include "params/PS2Mouse.hh"
+#include "sim/serialize.hh"
PS2Mouse::PS2Mouse(const PS2MouseParams &p)
: PS2Device(p),
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/serialize.hh"
using namespace std;
#include "debug/DiskImageRead.hh"
#include "debug/DiskImageWrite.hh"
#include "sim/byteswap.hh"
+#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
using namespace std;
#include "debug/VIO.hh"
#include "params/VirtIODeviceBase.hh"
#include "params/VirtIODummyDevice.hh"
+#include "sim/serialize.hh"
VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
#ifndef __DEV_VIRTIO_BASE_HH__
#define __DEV_VIRTIO_BASE_HH__
+#include <cstdint>
#include <functional>
+#include <vector>
#include "base/bitunion.hh"
+#include "base/types.hh"
#include "dev/virtio/virtio_ring.h"
#include "mem/port_proxy.hh"
+#include "sim/serialize.hh"
#include "sim/sim_object.hh"
struct VirtIODeviceBaseParams;
#include "mem/mem_checker.hh"
-#include <cassert>
+#include "base/logging.hh"
void
MemChecker::WriteCluster::startWrite(MemChecker::Serial serial, Tick _start,
++numIncomplete;
if (complete != TICK_FUTURE) {
- // Reopen a closed write cluster
- assert(_start < complete); // should open a new write cluster, instead;
- // also somewhat fishy wrt causality / ordering of calls vs time
+ // Reopen a closed write cluster
+ assert(_start < complete); // Should open a new write cluster instead
+ // Also somewhat fishy wrt causality / ordering of calls vs time
// progression TODO: Check me!
complete = TICK_FUTURE;
}
}
void
-MemChecker::WriteCluster::completeWrite(MemChecker::Serial serial, Tick _complete)
+MemChecker::WriteCluster::completeWrite(MemChecker::Serial serial,
+ Tick _complete)
{
auto it = writes.find(serial);
if (it == writes.end()) {
- warn("Could not locate write transaction: serial = %d, complete = %d\n",
- serial, _complete);
+ warn("Could not locate write transaction: serial = %d, "
+ "complete = %d\n", serial, _complete);
return;
}
// All writes have completed, this cluster is now complete and will be
// assigned the max of completion tick values among all writes.
//
- // Note that we cannot simply keep updating complete, because that would
- // count the cluster as closed already. Instead, we keep TICK_FUTURE
- // until all writes have completed.
+ // Note that we cannot simply keep updating complete, because that
+ // would count the cluster as closed already. Instead, we keep
+ // TICK_FUTURE until all writes have completed.
complete = completeMax;
}
}
}
bool
-MemChecker::ByteTracker::inExpectedData(Tick start, Tick complete, uint8_t data)
+MemChecker::ByteTracker::inExpectedData(Tick start, Tick complete,
+ uint8_t data)
{
_lastExpectedData.clear();
}
void
-MemChecker::ByteTracker::completeWrite(MemChecker::Serial serial, Tick complete)
+MemChecker::ByteTracker::completeWrite(MemChecker::Serial serial,
+ Tick complete)
{
getIncompleteWriteCluster()->completeWrite(serial, complete);
pruneTransactions();
// Pruning of readObservations
readObservations.erase(readObservations.begin(),
- lastCompletedTransaction(&readObservations, before));
+ lastCompletedTransaction(&readObservations, before));
// Pruning of writeClusters
if (!writeClusters.empty()) {
#ifndef __MEM_MEM_CHECKER_HH__
#define __MEM_MEM_CHECKER_HH__
+#include <cassert>
+#include <cstdint>
#include <list>
#include <map>
#include <string>
#include <unordered_map>
#include <vector>
-#include "base/logging.hh"
+#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/MemChecker.hh"
#include "mem/mem_interface.hh"
#include "base/bitfield.hh"
+#include "base/cprintf.hh"
#include "base/trace.hh"
#include "debug/DRAM.hh"
#include "debug/DRAMPower.hh"
#include "debug/AddrRanges.hh"
#include "debug/Checkpoint.hh"
#include "mem/abstract_mem.hh"
+#include "sim/serialize.hh"
/**
* On Linux, MAP_NORESERVE allow us to simulate a very large memory
#include <algorithm>
#include "base/cast.hh"
+#include "base/cprintf.hh"
#include "base/random.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include <algorithm>
#include <functional>
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/ClockDomain.hh"
#include "params/ClockDomain.hh"
#include "params/DerivedClockDomain.hh"
#include "params/SrcClockDomain.hh"
#include "sim/clocked_object.hh"
+#include "sim/serialize.hh"
#include "sim/voltage_domain.hh"
ClockDomain::ClockDomainStats::ClockDomainStats(ClockDomain &cd)
#include <set>
#include <utility>
-#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/DVFS.hh"
#include "params/DVFSHandler.hh"
-#include "sim/clock_domain.hh"
-#include "sim/eventq.hh"
+#include "sim/serialize.hh"
#include "sim/stat_control.hh"
#include "sim/voltage_domain.hh"
#ifndef __SIM_DVFS_HANDLER_HH__
#define __SIM_DVFS_HANDLER_HH__
+#include <cassert>
+#include <map>
#include <vector>
+#include "base/logging.hh"
+#include "base/types.hh"
#include "debug/DVFS.hh"
#include "params/DVFSHandler.hh"
#include "sim/clock_domain.hh"
#include <climits>
#include <functional>
#include <iosfwd>
+#include <list>
#include <memory>
#include <string>
#include "sim/linear_solver.hh"
#include "sim/power/thermal_model.hh"
#include "sim/probe/probe.hh"
+#include "sim/serialize.hh"
#include "sim/sub_system.hh"
ThermalDomain::ThermalDomain(const Params &p)
#include "sim/clocked_object.hh"
#include "sim/linear_solver.hh"
#include "sim/power/thermal_domain.hh"
+#include "sim/serialize.hh"
#include "sim/sim_object.hh"
/**
#include "sim/power_state.hh"
+#include <cassert>
+
#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/PowerDomain.hh"
#include "sim/power_domain.hh"
+#include "sim/serialize.hh"
PowerState::PowerState(const PowerStateParams &p) :
SimObject(p), _currState(p.default_state),
#define __SIM_POWER_STATE_HH__
#include <set>
+#include <vector>
#include "base/callback.hh"
#include "base/statistics.hh"
#include <unistd.h>
+#include "base/str.hh"
+
static std::string
normalizePath(std::string path)
{
#include "base/statistics.hh"
#include "base/time.hh"
+#include "base/types.hh"
#include "params/Root.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include <iostream>
-#include <iterator>
#include <type_traits>
+#include <utility>
#include "base/str.hh"
#ifndef __SIM_EXIT_HH__
#define __SIM_EXIT_HH__
+#include <functional>
#include <string>
#include "base/types.hh"
#include "params/TickedObject.hh"
#include "sim/clocked_object.hh"
+#include "sim/serialize.hh"
Ticked::Ticked(ClockedObject &object_,
Stats::Scalar *imported_num_cycles,
#include <algorithm>
-#include "base/statistics.hh"
+#include "base/logging.hh"
#include "base/trace.hh"
#include "debug/VoltageDomain.hh"
#include "params/VoltageDomain.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"
VoltageDomain::VoltageDomain(const Params &p)
: SimObject(p), voltageOpPoints(p.voltage), _perfLevel(0), stats(*this)