[PATCH] aarch64: Update missing ChangeLog for AArch64 commits

Patch with missing ChangeLog entries for GAS AArch64 files.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 94c8e3b3b589ef858766e274d02b9b4c18157964..5ba165075cb65ddd2090bb2a685efc97c7b1f038 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -158,6 +158,10 @@
        * elflink.c (bfd_elf_gc_sections): Do not arbitrarily keep note
        sections which are linked to another section.
 
+2020-09-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * cpu-arm.c: Add cortex-a78 and cortex-a78ae.
+
 2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * cpu-arm.c: (processors) Add Cortex-X1.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3c2d6891dc445d30bfe9d7ff932d231588120c71..77532859446b417fe0c52f2c2195c0956f8f51fc 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -25,6 +25,36 @@
        * testsuite/gas/i386/x86-64-property-11.d: Likewise.
        * testsuite/gas/i386/x86-64-property-12.d: Likewise.
 
+2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Update docs.
+       * testsuite/gas/aarch64/system-5.d: Update test with WFIT insn.
+       * testsuite/gas/aarch64/system-5.s: Update test with WFIT insn.
+
+2020-10-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Check for C0-C15 value of DSB
+       immediate string operand.
+       * testsuite/gas/aarch64/system-4.d: Update test.
+       * testsuite/gas/aarch64/system-4.s: Update test.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Update docs.
+       * config/tc-aarch64.c (parse_csr_operand): New operand parser.
+       (parse_operands): Call to CSR operand parser.
+       * testsuite/gas/aarch64/csre_csr-invalid.d: New test.
+       * testsuite/gas/aarch64/csre_csr-invalid.l: New test.
+       * testsuite/gas/aarch64/csre_csr-invalid.s: New test.
+       * testsuite/gas/aarch64/csre_csr.d: New test.
+       * testsuite/gas/aarch64/csre_csr.s: New test.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Update docs.
+       * testsuite/gas/aarch64/system-5.d: New test.
+       * testsuite/gas/aarch64/system-5.s: New test.
+
 2020-10-26  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/26778
@@ -63,6 +93,19 @@
        {vex3} to {vex}
        * testsuite/gas/i386/x86-64-avx-vnni.d: Likewise.
 
+2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Docs update.
+       * config/tc-aarch64.c (parse_operands): Add
+       AARCH64_OPND_BARRIER_DSB_NXS handler.
+       (md_begin): Add content of aarch64_barrier_dsb_nxs_options to
+       aarch64_barrier_opt_hsh hash.
+       * testsuite/gas/aarch64/system-4-invalid.d: New test.
+       * testsuite/gas/aarch64/system-4-invalid.l: New test.
+       * testsuite/gas/aarch64/system-4-invalid.s: New test.
+       * testsuite/gas/aarch64/system-4.d: New test.
+       * testsuite/gas/aarch64/system-4.s: New test.
+
 2020-10-21  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 
        PR target/26763
@@ -129,6 +172,19 @@
        * testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
        dwarf5-line-3.
 
+gas/ChangeLog:
+
+2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Docs update.
+       * config/tc-aarch64.c (armv8.7-a): New arch.
+       * doc/c-aarch64.texi (-march=armv8.7-a): Update docs.
+
+2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * testsuite/gas/aarch64/sysreg-6.d: New test.
+       * testsuite/gas/aarch64/sysreg-6.s: New test.
+
 2020-10-16  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/25878
@@ -251,6 +307,24 @@
        * testsuite/gas/i386/x86-64-property-14.d: Likewise.
        * testsuite/gas/i386/x86-64-property-14.s: Likewise.
 
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Docs update.
+       * testsuite/gas/aarch64/brbe-invalid.d: New test.
+       * testsuite/gas/aarch64/brbe-invalid.l: New test.
+       * testsuite/gas/aarch64/brbe-invalid.s: New test.
+       * testsuite/gas/aarch64/brbe.d: New test.
+       * testsuite/gas/aarch64/brbe.s: New test.
+
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * NEWS: Docs update.
+       * testsuite/gas/aarch64/csre-invalid.d: New test.
+       * testsuite/gas/aarch64/csre-invalid.l: New test.
+       * testsuite/gas/aarch64/csre-invalid.s: New test.
+       * testsuite/gas/aarch64/csre.d: New test.
+       * testsuite/gas/aarch64/csre.s: New test.
+
 2020-10-06  Alex Coplan  <alex.coplan@arm.com>
 
        PR 26699
@@ -276,6 +350,10 @@
        * testsuite/gas/elf/sh-link-zero.s: Don't start directives in
        first column.  Don't use numeric labels.
 
+2020-10-05  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * config/tc-arm.c: Update Cortex-X1 feature flags.
+
 2020-10-05  Kamil Rytarowski  <n54@gmx.com>
 
        * configure.tgt (aarch64*-*-netbsd*): Add target.
@@ -329,6 +407,10 @@
        * testsuite/gas/elf/section21.l: Updated expected assembler
        output.
 
+2020-10-05  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * config/tc-aarch64.c: Update Cortex-X1 feature flags.
+
 2020-10-03  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/26685
@@ -412,6 +494,14 @@
        avoid shadowing warning.
        * symbols.c (symbol_entry_find): Init all symbol_flags fields.
 
+2020-09-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * config/tc-arm.c: Add cortex-a78 and cortex-a78ae cores.
+       * doc/c-arm.texi: Update docs.
+       * NEWS: Update news.
+       * testsuite/gas/arm/cpu-cortex-a78.d: New test.
+       * testsuite/gas/arm/cpu-cortex-a78ae.d: New test.
+
 2020-09-29  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 
        * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.

diff --git a/include/ChangeLog b/include/ChangeLog
index afa52a33525f6a5eeff07695beec1ffee8215401..d11f36f272a1ada29e396ef81cb412bfeb8110e7 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -6,12 +6,23 @@
        (GNU_PROPERTY_X86_ISA_1_V3): Likewise.
        (GNU_PROPERTY_X86_ISA_1_V4): Likewise.
 
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
+\e(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
+
 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 
        * opcode/csky.h (CSKY_VERSION_V1): New, currently used.
        (CSKY_VERSION_V2): New.
        (CSKY_VERSION_V3): New.
 
+2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * opcode/aarch64.h (enum aarch64_opnd): New operand
+       AARCH64_OPND_BARRIER_DSB_NXS.
+       (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.
+
 2020-10-21  Tom Tromey  <tromey@adacore.com>
 
        * ctf-api.h (_CTF_ERRORS): New macro.
@@ -20,6 +31,11 @@
 
        * elf/riscv.h: Add R_RISCV_IRELATIVE to 58.
 
+2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
+       (AARCH64_ARCH_V8_7): New arch feature set.
+
 2020-10-09  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/26703

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 94659f4c3858712227905f2208e2ff38a8aa9331..cede9298a38f08f070920e875e039352d38580f4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,28 @@
+2020-10-30  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch65-tbl.h (struct aarch64_opcode): New instruction WFIT.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
+       * aarch64-tbl.h (CSRE): New CSRE feature handler.
+       (_CSRE_INSN): New CSRE instruction type.
+       (struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
+       and operand description.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
 2020-10-26  Cooper Qu <cooper.qu@linux.alibaba.com>
 
        * csky-opc.h (csky_v2_opcodes): Change plsl.u16 to plsl.16.
@@ -14,6 +39,23 @@
 
        * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. 
 
+2020-10-23  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
+       * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
+       ins_barrier_dsb_nx.
+       * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
+       * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
+       ext_barrier_dsb_nx.
+       * aarch64-opc.c (aarch64_print_operand): New options table
+       aarch64_barrier_dsb_nxs_options.
+       * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
+       * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
+       Armv8.7-a instruction.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
 2020-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 
        * po/es.po: Remove the duplicated entry.
@@ -46,6 +88,10 @@
        * i386-init.h: Regenerated.
        * i386-tbl.h: Likewise.
 
+2020-10-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-tbl.h (ARMV8_7): New macro.
+
 2020-10-14  H.J. Lu  <hongjiu.lu@intel.com>
            Lili Cui  <lili.cui@intel.com>
 
@@ -144,6 +190,14 @@
        Use Prefix_0XF3 on cvtdq2pd.  Use Prefix_0XF2 on cvtpd2dq.
        * i386-tbl.h: Regenerated.
 
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add BRBE system registers.
+
+2020-10-08  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: New CSRE system registers defined.
+
 2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
 
        * cgen-asm.c: Fix spelling mistakes.