init_1.c: Remove options -O2 -fno-schedule-insns and instead pass -O.

2019-06-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

	* gcc.target/aarch64/sve/init_1.c: Remove options
	-O2 -fno-schedule-insns and instead pass -O.
	Update assembly in comments.
	* gcc.target/aarch64/sve/init_2.c: Likewise.
	* gcc.target/aarch64/sve/init_3.c: Likewise.
	* gcc.target/aarch64/sve/init_4.c: Likewise.
	* gcc.target/aarch64/sve/init_5.c: Likewise and additionally
	adjust dg-scan.
	* gcc.target/aarch64/sve/init_6.c: Likewise.
	* gcc.target/aarch64/sve/init_7.c: Likewise.
	* gcc.target/aarch64/sve/init_8.c: Likewise.
	* gcc.target/aarch64/sve/init_9.c: Likewise.
	* gcc.target/aarch64/sve/init_10.c: Likewise.
	* gcc.target/aarch64/sve/init_11.c: Likewise.
	* gcc.target/aarch64/sve/init_12.c: Likewise.

From-SVN: r272073

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 217c5496542b7ac574b385b284a89733136f5409..372b06bc1af6d4ebcaf2778d3be3f2e8f4ea3b2e 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,21 @@
+2019-06-08  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>
+
+       * gcc.target/aarch64/sve/init_1.c: Remove options
+       -O2 -fno-schedule-insns and instead pass -O.
+       Update assembly in comments. 
+       * gcc.target/aarch64/sve/init_2.c: Likewise.
+       * gcc.target/aarch64/sve/init_3.c: Likewise.
+       * gcc.target/aarch64/sve/init_4.c: Likewise.
+       * gcc.target/aarch64/sve/init_5.c: Likewise and additionally
+       adjust dg-scan.
+       * gcc.target/aarch64/sve/init_6.c: Likewise.
+       * gcc.target/aarch64/sve/init_7.c: Likewise.
+       * gcc.target/aarch64/sve/init_8.c: Likewise.
+       * gcc.target/aarch64/sve/init_9.c: Likewise.
+       * gcc.target/aarch64/sve/init_10.c: Likewise.
+       * gcc.target/aarch64/sve/init_11.c: Likewise.
+       * gcc.target/aarch64/sve/init_12.c: Likewise.
+
 2019-06-07  Marek Polacek  <polacek@redhat.com>
 
        PR c++/77747

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
index 5c14b603f46eadaf79cf319b61287fd8d30426ef..14abc22e2cb7dbec93c7365b7ec2d59a0c7cd018 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 1.1: Trailing constants with stepped sequence.  */
 
@@ -17,7 +17,6 @@ vnx4si foo(int a, int b)
 foo:
 .LFB0:
         .cfi_startproc
-        ptrue   p0.s, vl8
         index   z0.s, #1, #1
         insr    z0.s, w1
         insr    z0.s, w0

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_10.c b/gcc/testsuite/gcc.target/aarch64/sve/init_10.c
index 9d6e2dfc876362c4401018ed2e4cb9f2df169c69..c83debe4dac89c18e78ee504fb9e5fa0ef2edd7f 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_10.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_10.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.4: Interleaved repeating elements and non-repeating elements.  */
 
@@ -17,13 +17,12 @@ vnx4si foo(int a, int b, int c, int f)
 foo:
 .LFB0:
         .cfi_startproc
-        mov     z0.s, w2
         mov     z1.s, w3
+        mov     z0.s, w2
         insr    z0.s, w1
-        ptrue   p0.s, vl8
         insr    z0.s, w0
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tmov\t(z[0-9]+\.s), w2\n.*\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_11.c b/gcc/testsuite/gcc.target/aarch64/sve/init_11.c
index e50cd54ef133bb766e70b6c6265b066800983fd8..90627b44efc7362a606275da4d8f22304d0be83e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_11.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_11.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.5: Interleaved repeating elements and trailing same elements.  */
 
@@ -18,11 +18,10 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w1
-        mov     z1.s, w2
         insr    z0.s, w0
-        ptrue   p0.s, vl8
+        mov     z1.s, w2
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w1\n\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w0\n.*\tzip1\t\1, \1, \2} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w1\n\tinsr\t\1, w0\n\tmov\t(z[0-9]+\.s), w2\n\tzip1\t\1, \1, \2} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
index 21d9e764360c487ff3a28dcc853ea4affd2b90df..dc20e86c02cf52f67c36c78b3796db25662d5758 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_12.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.5: Interleaved repeating elements and trailing same elements.  */
 
@@ -17,14 +17,13 @@ vnx4si foo(int a, int b, int f)
 foo:
 .LFB0:
         .cfi_startproc
-        mov     z0.s, w0
         mov     z1.s, w2
+        mov     z0.s, w0
         insr    z0.s, w1
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w1
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tmov\t(z[0-9]+\.s), w0\n.*\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tzip1\t\2, \2, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tmov\t(z[0-9]+\.s), w0\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tinsr\t\2, w1\n\tzip1\t\2, \2, \1} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_2.c b/gcc/testsuite/gcc.target/aarch64/sve/init_2.c
index a8b2a25b325440d0115646981a8ecdc84133c54a..5b4ba105af26ef975d5b6b222540e94f95c17bd2 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_2.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 1.2: Trailing constants with repeating sequence.  */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_3.c b/gcc/testsuite/gcc.target/aarch64/sve/init_3.c
index 6b000b887ba8a813859cd6c45f87f0b48daaca6d..28d218cd768eea9ffe25e4bfa3a9242d686b6ee8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_3.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 2.1: Leading constants with stepped sequence.  */
 
@@ -17,7 +17,6 @@ vnx4si foo(int a, int b)
 foo:
 .LFB0:
         .cfi_startproc
-        ptrue   p0.s, vl8
         index   z0.s, #6, #-1
         insr    z0.s, w0
         insr    z0.s, w1

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_4.c b/gcc/testsuite/gcc.target/aarch64/sve/init_4.c
index 619274928e47ea50dd3a933ebac322c5c2073137..94484b1a4e66b7e877bc5cb474df9583ac246cf5 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_4.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 2.2: Leading constants with stepped sequence.  */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_5.c b/gcc/testsuite/gcc.target/aarch64/sve/init_5.c
index e7fbdd1a2aaff0c033f4b47d819e7a6614349239..a43dd7a4ac7ceb49a134e2759fc8de57370a0d30 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_5.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 3: Trailing same element.  */ 
 
@@ -18,10 +18,9 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w2
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w0
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n.*\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_6.c b/gcc/testsuite/gcc.target/aarch64/sve/init_6.c
index f6f3da5958db01947effb9b84860b4a79a6ab3ec..b8e30fb72ebd10a949ed91163613f8f7cdfd17a3 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_6.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_6.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 3: Trailing same element.  */ 
 
@@ -18,11 +18,10 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w2
-        ptrue   p0.s, vl8
         insr    z0.s, w1
         insr    z0.s, w0
         rev     z0.s, z0.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n.*\tinsr\t\1, w1\n\tinsr\t\1, w0\n\trev\t\1, \1} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0\n\trev\t\1, \1} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_7.c b/gcc/testsuite/gcc.target/aarch64/sve/init_7.c
index e3104a35f1387cffc92554d67265a5afd9b79134..dd27978faf7e676bd1859f9347a7b1b038694c29 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_7.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_7.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.1: All elements.  */ 
 
@@ -18,7 +18,6 @@ foo:
 .LFB0:
         .cfi_startproc
         mov     z0.s, w7
-        ptrue   p0.s, vl8
         insr    z0.s, w6
         insr    z0.s, w5
         insr    z0.s, w4
@@ -29,4 +28,4 @@ foo:
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w7\n.*\tinsr\t\1, w6\n\tinsr\t\1, w5\n\tinsr\t\1, w4\n\tinsr\t\1, w3\n\tinsr\t\1, w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w7\n\tinsr\t\1, w6\n\tinsr\t\1, w5\n\tinsr\t\1, w4\n\tinsr\t\1, w3\n\tinsr\t\1, w2\n\tinsr\t\1, w1\n\tinsr\t\1, w0} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_8.c b/gcc/testsuite/gcc.target/aarch64/sve/init_8.c
index 7ff3e0849cc5294dea3f50c1fa315f2e3bbd7202..73f7aba3df3d8fa973cbf35c268f8c45760d817a 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_8.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.2: Interleaved elements and constants.  */ 
 
@@ -18,15 +18,15 @@ foo:
 .LFB0:
         .cfi_startproc
         ptrue   p0.s, vl8
+        adrp    x4, .LANCHOR0
+        add     x4, x4, :lo12:.LANCHOR0
+        ld1w    z1.s, p0/z, [x4]
         mov     z0.s, w3
-        adrp    x3, .LANCHOR0
         insr    z0.s, w2
-        add     x3, x3, :lo12:.LANCHOR0
         insr    z0.s, w1
-        ld1w    z1.s, p0/z, [x3]
         insr    z0.s, w0
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tadrp\t(x[0-9]+), \.LANCHOR0\n\tinsr\t\1, w2\n\tadd\t\2, \2, :lo12:\.LANCHOR0\n\tinsr\t\1, w1\n\tld1w\t(z[0-9]+\.s), p[0-9]+/z, \[\2\]\n\tinsr\t\1, w0\n\tzip1\t\1, \1, \3} } } */
+/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+\.s), p[0-9]+/z, \[x[0-9]+\]\n\tmov\t(z[0-9]+\.s), w3\n\tinsr\t\2, w2\n\tinsr\t\2, w1\n\tinsr\t\2, w0\n\tzip1\t\2, \2, \1} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_9.c b/gcc/testsuite/gcc.target/aarch64/sve/init_9.c
index 4d3c59b3bf806c943bb27cb43794e20316577307..2cc564a5a8395b06b8b0ad12c53524e5ac704fe6 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/init_9.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_9.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
 
 /* Case 5.3: Repeated elements.  */ 
 
@@ -19,9 +19,8 @@ foo:
         .cfi_startproc
         mov     z0.s, w0
         mov     z1.s, w1
-        ptrue   p0.s, vl8
         zip1    z0.s, z0.s, z1.s
         ret
 */
 
-/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w0\n\tmov\t(z[0-9]+\.s), w1\n.*\tzip1\t\1, \1, \2} } } */
+/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w0\n\tmov\t(z[0-9]+\.s), w1\n\tzip1\t\1, \1, \2} } } */