* gas/ppc/altivec_xcoff64.s: Likewise.
* gas/ppc/booke_xcoff64.s: Likewise.
* gas/ppc/altivec_xcoff.d: Accept 32bits offsets.
* gas/ppc/booke_xcoff.s: Do not use .machine pseudo-op and remove
* booke64 opcodes.
* gas/ppc/booke_xcoff.d: Accept 32bits offsets and renumber.
* gas/ppc/booke_xcoff64.d: Use booke opcodes.
+2007-10-01 Tristan Gingold <gingold@adacore.com>
+
+ * gas/ppc/altivec_xcoff.s: Do not use .machine pseudo-ops as it
+ overrides gas options.
+ * gas/ppc/altivec_xcoff64.s: Likewise.
+ * gas/ppc/booke_xcoff64.s: Likewise.
+ * gas/ppc/altivec_xcoff.d: Accept 32bits offsets.
+ * gas/ppc/booke_xcoff.s: Do not use .machine pseudo-op and remove
+ booke64 opcodes.
+ * gas/ppc/booke_xcoff.d: Accept 32bits offsets and renumber.
+ * gas/ppc/booke_xcoff64.d: Use booke opcodes.
+
2007-09-30 H.J. Lu <hongjiu.lu@intel.com>
PR gas/5080
Disassembly of section .text:
-0000000000000000 <.text>:
+(00000000)?00000000 <.text>:
0: 7c 60 06 6c dss 3
4: 7e 00 06 6c dssall
8: 7c 25 22 ac dst r5,r4,1
# PowerPC xcoff AltiVec tests
#as: -mppc -maltivec
- .machine "ppc"
.csect .text[PR]
.csect main[DS]
main:
# PowerPC xcoff64 AltiVec tests
#as: -a64 -mppc64 -maltivec
- .machine "ppc64"
.csect .text[PR]
.csect main[DS]
main:
Disassembly of section .text:
-0000000000000000 <.text>:
+(00000000)?00000000 <.text>:
0: 7c 22 3f 64 tlbre r1,r2,7
4: 7c be 1f a4 tlbwe r5,r30,3
8: 7c a8 48 2c icbt 5,r8,r9
c: 7c a6 02 26 mfapidi r5,r6
10: 7c 07 46 24 tlbivax r7,r8
- 14: 7c 09 56 26 tlbivaxe r9,r10
- 18: 7c 0b 67 24 tlbsx r11,r12
- 1c: 7c 0d 77 26 tlbsxe r13,r14
- 20: 7e 80 04 40 mcrxr64 cr5
- 24: 4c 00 00 66 rfci
- 28: 7c 60 01 06 wrtee r3
- 2c: 7c 00 81 46 wrteei 1
- 30: 7c 85 02 06 mfdcrx r4,r5
- 34: 7c aa 3a 86 mfdcr r5,234
- 38: 7c e6 03 06 mtdcrx r6,r7
- 3c: 7d 10 6b 86 mtdcr 432,r8
- 40: 7c 00 04 ac sync
- 44: 7c 09 55 ec dcba r9,r10
- 48: 7c 00 06 ac eieio
+ 14: 7c 0b 67 24 tlbsx r11,r12
+ 18: 4c 00 00 66 rfci
+ 1c: 7c 60 01 06 wrtee r3
+ 20: 7c 00 81 46 wrteei 1
+ 24: 7c 85 02 06 mfdcrx r4,r5
+ 28: 7c aa 3a 86 mfdcr r5,234
+ 2c: 7c e6 03 06 mtdcrx r6,r7
+ 30: 7d 10 6b 86 mtdcr 432,r8
+ 34: 7c 00 04 ac msync
+ 38: 7c 09 55 ec dcba r9,r10
+ 3c: 7c 00 06 ac mbar
# Motorola PowerPC BookE tests
-#as: -mppc32 -mbooke32
- .machine "ppc32"
+#as: -mbooke32
.csect .text[PR]
.csect main[DS]
main:
icbt 5, 8, 9
mfapidi 5, 6
tlbivax 7, 8
- tlbivaxe 9, 10
tlbsx 11, 12
- tlbsxe 13, 14
- mcrxr64 5
rfci
wrtee 3
wrteei 1
c: 24 46 00 3d bcel 2,4\*cr1\+eq,48 <.text\+0x48>
10: 24 67 00 5a bcea 3,4\*cr1\+so,58 <.text\+0x58>
12: R_BA_16 .text
- 14: 24 88 00 7b bcela 4,4\*cr2,78 <.text\+0x78>
+ 14: 24 88 00 7b bcela 4,4\*cr2\+lt,78 <.text\+0x78>
16: R_BA_16 .text
18: 4c a9 00 22 bclre 5,4\*cr2\+gt
1c: 4c aa 00 23 bclrel 5,4\*cr2\+eq
20: 4d 0b 04 22 bcctre 8,4\*cr2\+so
- 24: 4d 0c 04 23 bcctrel 8,4\*cr3
+ 24: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
28: 58 00 00 74 be 9c <.text\+0x9c>
2c: 58 00 00 89 bel b4 <.text\+0xb4>
30: 58 00 00 f2 bea f0 <.text\+0xf0>
1a8: 7c aa 3a 86 mfdcr r5,234
1ac: 7c e6 03 06 mtdcrx r6,r7
1b0: 7d 10 6b 86 mtdcr 432,r8
- 1b4: 7c 00 04 ac sync
+ 1b4: 7c 00 04 ac msync
1b8: 7c 09 55 ec dcba r9,r10
- 1bc: 7c 00 06 ac eieio
+ 1bc: 7c 00 06 ac mbar
# Motorola PowerPC BookE tests
#as: -a64 -mppc64 -mbooke64
- .machine "ppc64"
.csect .text[PR]
.csect main[DS]
main:
Sections:
Idx Name Size VMA LMA File off Algn
- 0 \.text 00000004 0000000000000000 0000000000000000 000000a8 2\*\*2
+ 0 \.text 00000004 0+0 0+0 000000a8 2\*\*2
CONTENTS, ALLOC, LOAD, CODE
- 1 \.data 00000008 0000000000000004 0000000000000004 000000ac 2\*\*3
+ 1 \.data 00000008 0+04 0+04 000000ac 2\*\*3
CONTENTS, ALLOC, LOAD, RELOC, DATA
- 2 \.bss 00000000 000000000000000c 000000000000000c 00000000 2\*\*3
+ 2 \.bss 00000000 0+0c 0+0c 00000000 2\*\*3
ALLOC