arch-gcn3: ds_read_u8 and ds_read_u16 fix

This changeset zero extends the destination register
for ds_read_u8 and ds_read_u16 instructions.

Change-Id: I193adadd68adf2572b59743b1504f18ad225f506
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29951
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
index 8b72e0da163537182015f6193168006b7510cb61..6e5ff42448999d6d880abe2685c0faf2c6cd03b0 100644 (file)
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -32016,11 +32016,11 @@ namespace Gcn3ISA
     void
     Inst_DS__DS_READ_U8::completeAcc(GPUDynInstPtr gpuDynInst)
     {
-        VecOperandU8 vdst(gpuDynInst, extData.VDST);
+        VecOperandU32 vdst(gpuDynInst, extData.VDST);
 
         for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
             if (gpuDynInst->exec_mask[lane]) {
-                vdst[lane] = (reinterpret_cast<VecElemU8*>(
+                vdst[lane] = (VecElemU32)(reinterpret_cast<VecElemU8*>(
                     gpuDynInst->d_data))[lane];
             }
         }
@@ -32096,11 +32096,11 @@ namespace Gcn3ISA
     void
     Inst_DS__DS_READ_U16::completeAcc(GPUDynInstPtr gpuDynInst)
     {
-        VecOperandU16 vdst(gpuDynInst, extData.VDST);
+        VecOperandU32 vdst(gpuDynInst, extData.VDST);
 
         for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
             if (gpuDynInst->exec_mask[lane]) {
-                vdst[lane] = (reinterpret_cast<VecElemU16*>(
+                vdst[lane] = (VecElemU32)(reinterpret_cast<VecElemU16*>(
                     gpuDynInst->d_data))[lane];
             }
         }