ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 7d58350a47f21ac9d851378fdb4e59b3e40f9dc8..8d386b0b001855911810fdf14382764498dba0aa 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -122,6 +122,12 @@ def format McrMrc15() {{
           case MISCREG_BPIMVA:
             return new WarnUnimplemented(
                     isRead ? "mrc bpimva" : "mcr bpimva", machInst);
+          case MISCREG_BPIALLIS:
+            return new WarnUnimplemented(
+                    isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
+          case MISCREG_BPIALL:
+            return new WarnUnimplemented(
+                    isRead ? "mrc bpiall" : "mcr bpiall", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 49b015984fccb8dade7356f6a759965bc6bbbdbb..a43bb2fe52648906518d2a43523ca980a20247ad 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -100,6 +100,8 @@ namespace ArmISA
         MISCREG_ICIALLU,
         MISCREG_ICIMVAU,
         MISCREG_BPIMVA,
+        MISCREG_BPIALLIS,
+        MISCREG_BPIALL,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -135,8 +137,6 @@ namespace ArmISA
         MISCREG_DRACR,
         MISCREG_IRACR,
         MISCREG_RGNR,
-        MISCREG_BPIALLIS,
-        MISCREG_BPIALL,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
         MISCREG_MCCSW,
@@ -162,7 +162,8 @@ namespace ArmISA
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
         "clidr", "ccsidr", "csselr",
-        "icialluis", "iciallu", "icimvau", "bpimva",
+        "icialluis", "iciallu", "icimvau",
+        "bpimva", "bpiallis", "bpiall",
         "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@@ -170,8 +171,8 @@ namespace ArmISA
         "aidr", "actlr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
-        "rgnr", "bpiallis",
-        "bpiall", "dcimvac", "dcisw", "mccsw",
+        "rgnr",
+        "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nop", "raz"
     };