Add +/xilinx/cells_box.v containing models for ABC boxes

diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 432bb0770ae85ee3bdec257fcab32f740fa8e8ee..43be55d5140485980b29d6500f48f74f04adee78 100644 (file)
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))

diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v
new file mode 100644 (file)
index 0000000..7805e63
--- /dev/null
+++ b/techlibs/xilinx/cells_box.v
@@ -0,0 +1,10 @@
+(* abc_box_id = 1 *)
+module MUXF7(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+
+(* abc_box_id = 2 *)
+module MUXF8(output O, input I0, I1, S);
+  assign O = S ? I1 : I0;
+endmodule
+