i965: Disable 3DSTATE_WM_HZ_OP fields.

Eric believes this to be wrong and unnecessary, as the command is
supposed to emit an implicit rectangle primitive.  However, empirically
the pixel pipeline is completely unreliable without it.  So for now, it
stays until someone comes up with a better solution.

We'll need to do better than this when we implement multisampling, HiZ,
or fast clears...but for now, this will do.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index b29d0c44bb89118fa6ebac8fcb1729727fba23e9..75d09fc72b28220e7e1debe70f8fb4a4fff62f3e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1752,6 +1752,8 @@ enum brw_message_target {
 #define GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE         (1 << 1)
 #define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE        (1 << 0)
 
+#define _3DSTATE_WM_HZ_OP                       0x7852 /* GEN8+ */
+
 #define _3DSTATE_PS_BLEND                       0x784D /* GEN8+ */
 /* DW1 */
 # define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE         (1 << 31)

diff --git a/src/mesa/drivers/dri/i965/gen8_disable.c b/src/mesa/drivers/dri/i965/gen8_disable.c
index e1e26c6ac8e102d34da4533b04a861167ce3376d..276bd2e55fd12f1ee06f621e87a1513476ffe364 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_disable.c
+++ b/src/mesa/drivers/dri/i965/gen8_disable.c
@@ -29,6 +29,14 @@
 static void
 disable_stages(struct brw_context *brw)
 {
+   BEGIN_BATCH(5);
+   OUT_BATCH(_3DSTATE_WM_HZ_OP << 16 | (5 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+
    /* Disable the HS Unit */
    BEGIN_BATCH(11);
    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (11 - 2));