return _("NT_ARM_SVE (AArch SVE registers)");
       case NT_ARM_PAC_MASK:
        return _("NT_ARM_PAC_MASK (AArch pointer authentication code masks)");
+      case NT_ARM_PACA_KEYS:
+       return _("NT_ARM_PACA_KEYS (ARM pointer authentication address keys)");
+      case NT_ARM_PACG_KEYS:
+       return _("NT_ARM_PACG_KEYS (ARM pointer authentication generic keys)");
       case NT_ARM_TAGGED_ADDR_CTRL:
        return _("NT_ARM_TAGGED_ADDR_CTRL (AArch tagged address control)");
+      case NT_ARM_PAC_ENABLED_KEYS:
+       return _("NT_ARM_PAC_ENABLED_KEYS (AArch64 pointer authentication enabled keys)");
       case NT_ARC_V2:
        return _("NT_ARC_V2 (ARC HS accumulator/extra registers)");
       case NT_RISCV_CSR:
 
                                        /*   note name must be "LINUX".  */
 #define NT_ARM_PAC_MASK        0x406           /* AArch pointer authentication code masks */
                                        /*   note name must be "LINUX".  */
+#define NT_ARM_PACA_KEYS  0x407                /* ARM pointer authentication address
+                                          keys */
+                                       /*   note name must be "LINUX".  */
+#define NT_ARM_PACG_KEYS  0x408                /* ARM pointer authentication generic
+                                          keys */
+                                       /*  note name must be "LINUX".  */
 #define NT_ARM_TAGGED_ADDR_CTRL        0x409   /* AArch64 tagged address control
                                           (prctl()) */
                                        /*   note name must be "LINUX".  */
+#define NT_ARM_PAC_ENABLED_KEYS        0x40a   /* AArch64 pointer authentication
+                                          enabled keys (prctl()) */
+                                       /*   note name must be "LINUX".  */
 #define NT_ARC_V2      0x600           /* ARC HS accumulator/extra registers.  */
                                        /*   note name must be "LINUX".  */
 #define NT_RISCV_CSR    0x900          /* RISC-V Control and Status Registers */