added tests for new verilog features

diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v
new file mode 100644 (file)
index 0000000..ad50980
--- /dev/null
+++ b/tests/simple/arraycells.v
@@ -0,0 +1,15 @@
+
+module test001(a, b, c, y);
+       input a;
+       input [31:0] b, c;
+       input [31:0] y;
+
+       aoi12 p [31:0] (a, b, c, y);
+endmodule
+
+module aoi12(a, b, c, y);
+       input a, b, c;
+       output y;
+       assign y = ~((a & b) | c);
+endmodule
+

diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v
index 8c5b4b371b6acb455f32102b4091cce442b894f0..cde37c563e4e6a5cf4d36abb27360da6ac14b65c 100644 (file)
--- a/tests/simple/repwhile.v
+++ b/tests/simple/repwhile.v
@@ -1,4 +1,5 @@
-module test001(output [63:0] y);
+module test001(input [5:0] a, output [7:0] y, output [31:0] x);
+
        function [7:0] mylog2;
                input [31:0] value;
                begin
@@ -10,11 +11,26 @@ module test001(output [63:0] y);
                end
        endfunction
 
-       genvar i;
-       generate
+       function [31:0] myexp2;
+               input [7:0] value;
+               begin
+                       myexp2 = 1;
+                       repeat (value)
+                               myexp2 = myexp2 << 1;
+               end
+       endfunction
+
+       reg [7:0] y_table [63:0];
+       reg [31:0] x_table [63:0];
+
+       integer i;
+       initial begin
                for (i = 0; i < 64; i = i+1) begin
-                       localparam tmp = mylog2(i);
-                       assign y[i] = tmp;
+                       y_table[i] <= mylog2(i);
+                       x_table[i] <= myexp2(i);
                end
-       endgenerate
+       end
+
+       assign y = y_table[a];
+       assign x = x_table[a];
 endmodule