(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index d4d51299476252a2ecbf7d597c562b42d3dee711..aa9219501bc6cc87e5ecbfbabfe0b5d42171fcd5 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -655,9 +655,10 @@ One extremely important aspect of ffirst is:
 
 ## pred-result mode
 
-This mode merges common CR testing with predication, saving on instruction count
+This mode merges common CR testing with predication, saving on instruction count. Below is the pseudocode excluding predicate zeroing and elwidth overrides.
 
     for i in range(VL):
+        # predication test, skip all masked out elements.
         if predicate_masked_out(i):
              continue
         result = op(iregs[RA+i], iregs[RB+i])
@@ -674,6 +675,8 @@ This mode merges common CR testing with predication, saving on instruction count
 The reason for allowing the CR element to be stored is so that post-analysis
 of the CR Vector may be carried out.  For example: Saturation may have occurred (and been prevented from updating, by the test) but it is desirable to know *which* elements fail saturation.
 
+Note that predication is still respected: predicate zeroing is slightly different: elements that fail the CR test *or* are masked out are zero'd.
+
 ## CR Operations
 
 CRs are slightly more involved than INT or FP registers due to the