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i965: Cite the Ivybridge PRM for VS PIPE_CONTROL workarounds.
authorKenneth Graunke <kenneth@whitecape.org>
Wed, 10 Jul 2013 20:39:19 +0000 (13:39 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Tue, 16 Jul 2013 02:40:52 +0000 (19:40 -0700)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/intel_batchbuffer.c patch | blob | history

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index ab7a9a37031492e08fc6f7195dfea6444bc219b0..7f4121cb94318ff00daa53df34cd94429a3835f5 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -419,8 +419,8 @@ intel_emit_depth_stall_flushes(struct brw_context *brw)
 }
 
 /**
- * From the BSpec, volume 2a.03: VS Stage Input / State:
- * "[DevIVB] A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
+ * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
+ * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
  *  stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
  *  3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
  *  3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL needs