Call memory_dff before DSP mapping to reserve registers (fixes #1447)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b66c6bf57d6f15cceabead5be064fc880a9b31fc..c942126e1b250bc163f62315f92e58bccfa86d3d 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass
                        run("opt_expr");
                        run("opt_clean");
                        if (help_mode || dsp) {
+                               run("memory_dff");
                                run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
                                                "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
                                                "-D DSP_NAME=$__MUL16X16", "(if -dsp)");

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index f13740865d3fe6e937ec49a5503cb118236fd5f8..6f8254b59d7f23a5ab8fa175b14cdedaeb171c70 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -341,6 +341,7 @@ struct SynthXilinxPass : public ScriptPass
 
                if (check_label("map_dsp", "(skip if '-nodsp')")) {
                        if (!nodsp || help_mode) {
+                               run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first
                                // NB: Xilinx multipliers are signed only
                                run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 "
                                        "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 "    // Partial multipliers are intentionally