DRIVER_DEFINES = -DCOMPILE_R300 -DR200_MERGED=0 \
-DRADEON_COMMON=1 -DRADEON_COMMON_FOR_R300 \
-# -DRADEON_BO_TRACK_OPEN \
# -DRADEON_BO_TRACK_REF \
+# -DRADEON_BO_TRACK_OPEN \
-Wall
SYMLINKS = \
radeon_bo_legacy.h \
radeon_cs_legacy.h
+DRI_LIB_DEPS += -ldrm_radeon
+
##### TARGETS #####
include ../Makefile.template
#include "r300_mipmap_tree.h"
#include "r300_state.h"
#include "radeon_cs_legacy.h"
+#include "radeon_cs_gem.h"
+#include "radeon_reg.h"
+
+#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
+# define RADEON_ONE_REG_WR (1 << 15)
// Set this to 1 for extremely verbose debugging of command buffers
#define DEBUG_CMDBUF 0
*/
void r300EnsureCmdBufSpace(r300ContextPtr r300, int dwords, const char *caller)
{
- assert(dwords < r300->cmdbuf.size);
-
if ((r300->cmdbuf.cs->cdw + dwords + 128) > r300->cmdbuf.size ||
radeon_cs_need_flush(r300->cmdbuf.cs)) {
r300FlushCmdBuf(r300, caller);
struct r300_state_atom *atom;
int dwords;
- BEGIN_BATCH_NO_AUTOSTATE(4);
- OUT_BATCH(cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN));
- OUT_BATCH(cmdpacket0(R300_TX_INVALTAGS, 1));
+ cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
+ BEGIN_BATCH_NO_AUTOSTATE(2);
+ OUT_BATCH(cmdpacket0(r300->radeon.radeonScreen, R300_TX_INVALTAGS, 1));
OUT_BATCH(R300_TX_FLUSH);
- OUT_BATCH(cmdpacify());
END_BATCH();
+ end_3d(r300);
/* Emit actual atoms */
foreach(atom, &r300->hw.atomlist) {
r300PrintStateAtom(r300, atom);
}
if (atom->emit) {
- (*atom->emit)(r300);
+ (*atom->emit)(r300, atom);
} else {
BEGIN_BATCH_NO_AUTOSTATE(dwords);
OUT_BATCH_TABLE(atom->cmd, dwords);
r300->hw.all_dirty = GL_FALSE;
}
-#define packet0_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->packet0.count)
+static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
+{
+ if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ return ((((*pkt) >> 16) & 0x3FFF) + 1);
+ } else {
+ drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
+ return t->packet0.count;
+ }
+ return 0;
+}
+
#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
-static void emit_tex_offsets(r300ContextPtr r300)
+void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom)
+{
+ BATCH_LOCALS(r300);
+ drm_r300_cmd_header_t cmd;
+ uint32_t addr, ndw, i;
+
+ if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ uint32_t dwords;
+ dwords = (*atom->check) (r300, atom);
+ BEGIN_BATCH_NO_AUTOSTATE(dwords);
+ OUT_BATCH_TABLE(atom->cmd, dwords);
+ END_BATCH();
+ return;
+ }
+
+ cmd.u = atom->cmd[0];
+ addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
+ ndw = cmd.vpu.count * 4;
+ if (ndw) {
+ /* flush processing vertices */
+ OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
+ OUT_BATCH(0x0);
+ OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+ OUT_BATCH((1 << 15) | (1 << 28));
+ OUT_BATCH(CP_PACKET0(R300_SC_SCREENDOOR, 0));
+ OUT_BATCH(0x00FFFFFF);
+ OUT_BATCH(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
+ OUT_BATCH(1);
+ /* write vpu */
+ OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_ADDRESS, 0));
+ OUT_BATCH(addr);
+ OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
+ for (i = 0; i < ndw; i++) {
+ OUT_BATCH(atom->cmd[i+1]);
+ }
+ }
+}
+
+static void emit_tex_offsets(r300ContextPtr r300, struct r300_state_atom * atom)
{
BATCH_LOCALS(r300);
- int numtmus = packet0_count(r300->hw.tex.offset.cmd);
+ int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
if (numtmus) {
int i;
}
}
-static void emit_cb_offset(r300ContextPtr r300)
+static void emit_cb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
{
BATCH_LOCALS(r300);
struct radeon_renderbuffer *rrb;
uint32_t cbpitch;
+ GLframebuffer *fb = r300->radeon.dri.drawable->driverPrivate;
rrb = r300->radeon.state.color.rrb;
+ if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ rrb = fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ }
if (!rrb) {
fprintf(stderr, "no rrb\n");
return;
}
- cbpitch = rrb->pitch;
+ cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
cbpitch |= R300_COLOR_FORMAT_ARGB8888;
else
END_BATCH();
}
-static void emit_zb_offset(r300ContextPtr r300)
+static void emit_zb_offset(r300ContextPtr r300, struct r300_state_atom * atom)
{
BATCH_LOCALS(r300);
struct radeon_renderbuffer *rrb;
if (!rrb)
return;
- zbpitch = rrb->pitch;
+ zbpitch = (rrb->pitch / rrb->cpp);
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
zbpitch |= R300_DEPTHMACROTILE_ENABLE;
}
- if (r300->radeon.glCtx->Visual.depthBits == 24) {
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
zbpitch |= R300_DEPTHMICROTILE_TILED;
}
static int check_variable(r300ContextPtr r300, struct r300_state_atom *atom)
{
int cnt;
- cnt = packet0_count(atom->cmd);
+ if (atom->cmd[0] == CP_PACKET2) {
+ return 0;
+ }
+ cnt = packet0_count(r300, atom->cmd);
return cnt ? cnt + 1 : 0;
}
-static int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
+int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom)
{
int cnt;
+
cnt = vpu_count(atom->cmd);
return cnt ? (cnt * 4) + 1 : 0;
}
static int check_r500fp(r300ContextPtr r300, struct r300_state_atom *atom)
{
int cnt;
+
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 6) + 1 : 0;
}
static int check_r500fp_const(r300ContextPtr r300, struct r300_state_atom *atom)
{
int cnt;
- cnt = r500fp_count(atom->cmd);
+
+ cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 4) + 1 : 0;
}
/* Initialize state atoms */
ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
- r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(R300_SE_VPORT_XSCALE, 6);
+ r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(R300_VAP_PVS_STATE_FLUSH_REG, 1);
+ r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
- r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(R300_VAP_CNTL, 1);
+ r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
if (is_r500) {
ALLOC_STATE(vap_index_offset, always, 2, 0);
- r300->hw.vap_index_offset.cmd[0] = cmdpacket0(R500_VAP_INDEX_OFFSET, 1);
+ r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
r300->hw.vap_index_offset.cmd[1] = 0;
}
ALLOC_STATE(vte, always, 3, 0);
- r300->hw.vte.cmd[0] = cmdpacket0(R300_SE_VTE_CNTL, 2);
+ r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
- r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(R300_VAP_VF_MAX_VTX_INDX, 2);
+ r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
ALLOC_STATE(vap_cntl_status, always, 2, 0);
- r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(R300_VAP_CNTL_STATUS, 1);
+ r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
- cmdpacket0(R300_VAP_PROG_STREAM_CNTL_0, 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
- cmdpacket0(R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
- r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(R300_VAP_VTX_STATE_CNTL, 2);
+ r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
- r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
+ r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
if (has_tcl) {
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
- r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(R300_VAP_CLIP_CNTL, 1);
+ r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
- r300->hw.vap_clip.cmd[0] = cmdpacket0(R300_VAP_GB_VERT_CLIP_ADJ, 4);
+ r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
- r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(VAP_PVS_VTX_TIMEOUT_REG, 1);
+ r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
}
ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
r300->hw.vof.cmd[R300_VOF_CMD_0] =
- cmdpacket0(R300_VAP_OUTPUT_VTX_FMT_0, 2);
+ cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
if (has_tcl) {
ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
r300->hw.pvs.cmd[R300_PVS_CMD_0] =
- cmdpacket0(R300_VAP_PVS_CODE_CNTL_0, 3);
+ cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
}
ALLOC_STATE(gb_enable, always, 2, 0);
- r300->hw.gb_enable.cmd[0] = cmdpacket0(R300_GB_ENABLE, 1);
+ r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
- r300->hw.gb_misc.cmd[0] = cmdpacket0(R300_GB_MSPOS0, 5);
+ r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 5);
ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
- r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(R300_TX_ENABLE, 1);
+ r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
ALLOC_STATE(ga_point_s0, always, 5, 0);
- r300->hw.ga_point_s0.cmd[0] = cmdpacket0(R300_GA_POINT_S0, 4);
+ r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
- r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(R300_GA_TRIANGLE_STIPPLE, 1);
+ r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
- r300->hw.ps.cmd[0] = cmdpacket0(R300_GA_POINT_SIZE, 1);
+ r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
ALLOC_STATE(ga_point_minmax, always, 4, 0);
- r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(R300_GA_POINT_MINMAX, 3);
+ r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
ALLOC_STATE(lcntl, always, 2, 0);
- r300->hw.lcntl.cmd[0] = cmdpacket0(R300_GA_LINE_CNTL, 1);
+ r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
ALLOC_STATE(ga_line_stipple, always, 4, 0);
- r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(R300_GA_LINE_STIPPLE_VALUE, 3);
+ r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
ALLOC_STATE(shade, always, 5, 0);
- r300->hw.shade.cmd[0] = cmdpacket0(R300_GA_ENHANCE, 4);
+ r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 4);
ALLOC_STATE(polygon_mode, always, 4, 0);
- r300->hw.polygon_mode.cmd[0] = cmdpacket0(R300_GA_POLY_MODE, 3);
+ r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
ALLOC_STATE(fogp, always, 3, 0);
- r300->hw.fogp.cmd[0] = cmdpacket0(R300_GA_FOG_SCALE, 2);
+ r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
ALLOC_STATE(zbias_cntl, always, 2, 0);
- r300->hw.zbias_cntl.cmd[0] = cmdpacket0(R300_SU_TEX_WRAP, 1);
+ r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
- cmdpacket0(R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
+ cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
ALLOC_STATE(occlusion_cntl, always, 2, 0);
- r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(R300_SU_POLY_OFFSET_ENABLE, 1);
+ r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
- r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(R300_SU_CULL_MODE, 1);
+ r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
ALLOC_STATE(su_depth_scale, always, 3, 0);
- r300->hw.su_depth_scale.cmd[0] = cmdpacket0(R300_SU_DEPTH_SCALE, 2);
+ r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
- r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(R300_RS_COUNT, 2);
+ r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
if (is_r500) {
ALLOC_STATE(ri, always, R500_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R500_RS_IP_0, 16);
+ r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
for (i = 0; i < 8; i++) {
r300->hw.ri.cmd[R300_RI_CMD_0 + i +1] =
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT);
}
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, 1);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
} else {
ALLOC_STATE(ri, always, R300_RI_CMDSIZE, 0);
- r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(R300_RS_IP_0, 8);
+ r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, 1);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
}
ALLOC_STATE(sc_hyperz, always, 3, 0);
- r300->hw.sc_hyperz.cmd[0] = cmdpacket0(R300_SC_HYPERZ, 2);
+ r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
ALLOC_STATE(sc_screendoor, always, 2, 0);
- r300->hw.sc_screendoor.cmd[0] = cmdpacket0(R300_SC_SCREENDOOR, 1);
+ r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
ALLOC_STATE(us_out_fmt, always, 6, 0);
- r300->hw.us_out_fmt.cmd[0] = cmdpacket0(R300_US_OUT_FMT, 5);
+ r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
if (is_r500) {
ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(R500_US_CONFIG, 2);
+ r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
- r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(R500_US_CODE_ADDR, 3);
- r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(R500_US_FC_CTRL, 1);
+ r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
+ r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
- r300->hw.r500fp.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 0, 0);
+ r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
+ cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
- r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] = cmdr500fp(0, 0, 1, 0);
+ r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
+ cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
} else {
ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
- r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(R300_US_CONFIG, 3);
- r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(R300_US_CODE_ADDR_0, 4);
+ r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
+ r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
+
ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
- r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(R300_US_TEX_INST_0, 0);
+ r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
- r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, 1);
+ r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
- r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, 1);
+ r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
- r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, 1);
+ r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
- r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, 1);
+ r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
- r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, 0);
+ r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
}
ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
- r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(R300_FG_FOG_BLEND, 1);
+ r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
- r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(R300_FG_FOG_COLOR_R, 3);
+ r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
- r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(R300_FG_ALPHA_FUNC, 2);
+ r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
ALLOC_STATE(fg_depth_src, always, 2, 0);
- r300->hw.fg_depth_src.cmd[0] = cmdpacket0(R300_FG_DEPTH_SRC, 1);
+ r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
ALLOC_STATE(rb3d_cctl, always, 2, 0);
- r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(R300_RB3D_CCTL, 1);
+ r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
- r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(R300_RB3D_CBLEND, 2);
+ r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
- r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(RB3D_COLOR_CHANNEL_MASK, 1);
+ r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
if (is_r500) {
ALLOC_STATE(blend_color, always, 3, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(R500_RB3D_CONSTANT_COLOR_AR, 2);
+ r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
} else {
ALLOC_STATE(blend_color, always, 2, 0);
- r300->hw.blend_color.cmd[0] = cmdpacket0(R300_RB3D_BLEND_COLOR, 1);
+ r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
}
ALLOC_STATE(rop, always, 2, 0);
- r300->hw.rop.cmd[0] = cmdpacket0(R300_RB3D_ROPCNTL, 1);
+ r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, always, R300_CB_CMDSIZE, 0);
r300->hw.cb.emit = &emit_cb_offset;
ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
- r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(R300_RB3D_DITHER_CTL, 9);
+ r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
- r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(R300_RB3D_AARESOLVE_CTL, 1);
+ r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
- r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
+ r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
r300->hw.zs.cmd[R300_ZS_CMD_0] =
- cmdpacket0(R300_ZB_CNTL, 3);
+ cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
ALLOC_STATE(zstencil_format, always, 5, 0);
r300->hw.zstencil_format.cmd[0] =
- cmdpacket0(R300_ZB_FORMAT, 4);
+ cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
r300->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
- r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(R300_ZB_DEPTHCLEARVALUE, 1);
+ r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(unk4F30, always, 3, 0);
- r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2);
+ r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
- r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(R300_ZB_HIZ_OFFSET, 1);
+ r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
- r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(R300_ZB_HIZ_PITCH, 1);
+ r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {
int i;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
- r300->hw.vpi.cmd[R300_VPI_CMD_0] =
- cmdvpu(R300_PVS_CODE_START, 0);
+ r300->hw.vpi.cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
+ r300->hw.vpi.emit = emit_vpu;
if (is_r500) {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[R300_VPP_CMD_0] =
- cmdvpu(R500_PVS_CONST_START, 0);
+ r300->hw.vpp.cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
+ r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[R300_VPS_CMD_0] =
- cmdvpu(R500_POINT_VPORT_SCALE_OFFSET, 1);
+ r300->hw.vps.cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
+ r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
- cmdvpu(R500_PVS_UCP_START + i, 1);
+ r300->hw.vpucp[i].cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen,
+ R500_PVS_UCP_START + i, 1);
+ r300->hw.vpucp[i].emit = emit_vpu;
}
} else {
ALLOC_STATE(vpp, vpu, R300_VPP_CMDSIZE, 0);
- r300->hw.vpp.cmd[R300_VPP_CMD_0] =
- cmdvpu(R300_PVS_CONST_START, 0);
+ r300->hw.vpp.cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
+ r300->hw.vpp.emit = emit_vpu;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
- r300->hw.vps.cmd[R300_VPS_CMD_0] =
- cmdvpu(R300_POINT_VPORT_SCALE_OFFSET, 1);
+ r300->hw.vps.cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
+ r300->hw.vps.emit = emit_vpu;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
- r300->hw.vpucp[i].cmd[R300_VPUCP_CMD_0] =
- cmdvpu(R300_PVS_UCP_START + i, 1);
+ r300->hw.vpucp[i].cmd[0] =
+ cmdvpu(r300->radeon.radeonScreen,
+ R300_PVS_UCP_START + i, 1);
+ r300->hw.vpucp[i].emit = emit_vpu;
}
}
}
/* Textures */
ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER0_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER1_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
ALLOC_STATE(tex.size, variable, mtu + 1, 0);
- r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_SIZE_0, 0);
+ r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
ALLOC_STATE(tex.format, variable, mtu + 1, 0);
r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FORMAT_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
- r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(R300_TX_FORMAT2_0, 0);
+ r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
ALLOC_STATE(tex.offset, variable, 1, 0);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_OFFSET_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
r300->hw.tex.offset.emit = &emit_tex_offsets;
ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_CHROMA_KEY_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_BORDER_COLOR_0, 0);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
r300->hw.is_dirty = GL_TRUE;
r300->hw.all_dirty = GL_TRUE;
size * 4, r300->hw.max_state_size * 4);
}
- r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon);
+ if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ int fd = r300->radeon.radeonScreen->driScreen->fd;
+ r300->cmdbuf.csm = radeon_cs_manager_gem(fd);
+ } else {
+ r300->cmdbuf.csm = radeon_cs_manager_legacy(&r300->radeon);
+ }
if (r300->cmdbuf.csm == NULL) {
/* FIXME: fatal error */
return;
foreach(atom, &r300->hw.atomlist) {
FREE(atom->cmd);
}
+ if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
+ radeon_cs_manager_gem_shutdown(r300->cmdbuf.csm);
+ } else {
+ radeon_cs_manager_legacy_shutdown(r300->cmdbuf.csm);
+ }
}
*/
#define OUT_BATCH_RELOC(data, bo, offset, flags) \
do { \
+ if (offset) {\
+ fprintf(stderr, "(%s:%s:%d) offset : %d\n",\
+ __FILE__, __FUNCTION__, __LINE__, offset);\
+ }\
radeon_cs_write_dword(b_l_r300->cmdbuf.cs, offset);\
radeon_cs_write_reloc(b_l_r300->cmdbuf.cs,bo,0,(bo)->size,flags);\
} while(0)
do { \
} while(0)
+void emit_vpu(r300ContextPtr r300, struct r300_state_atom * atom);
+int check_vpu(r300ContextPtr r300, struct r300_state_atom *atom);
+
#endif /* __R300_CMDBUF_H__ */
GLboolean dirty;
int (*check) (r300ContextPtr, struct r300_state_atom * atom);
- void (*emit) (r300ContextPtr);
+ void (*emit) (r300ContextPtr, struct r300_state_atom * atom);
};
#define R300_VPT_CMD_0 0
aos->stride = size;
}
aos->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
- 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT);
+ 0, bo_size, 32, RADEON_GEM_DOMAIN_GTT, 0);
aos->offset = 0;
aos->components = size;
aos->count = count;
}
/* Setup INPUT_ROUTE. */
+ if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ R300_STATECHANGE(rmesa, vir[0]);
+ rmesa->hw.vir[0].cmd[0] &= 0xC000FFFF;
+ rmesa->hw.vir[1].cmd[0] &= 0xC000FFFF;
+ rmesa->hw.vir[0].cmd[0] |=
+ (r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
+ vb->AttribPtr, inputs, tab, nr) & 0x3FFF) << 16;
+ R300_STATECHANGE(rmesa, vir[1]);
+ rmesa->hw.vir[1].cmd[0] |=
+ (r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
+ nr) & 0x3FFF) << 16;
+ } else {
R300_STATECHANGE(rmesa, vir[0]);
((drm_r300_cmd_header_t *) rmesa->hw.vir[0].cmd)->packet0.count =
r300VAPInputRoute0(&rmesa->hw.vir[0].cmd[R300_VIR_CNTL_0],
((drm_r300_cmd_header_t *) rmesa->hw.vir[1].cmd)->packet0.count =
r300VAPInputRoute1(&rmesa->hw.vir[1].cmd[R300_VIR_CNTL_0], swizzle,
nr);
+ }
/* Setup INPUT_CNTL. */
R300_STATECHANGE(rmesa, vic);
/* TODO: move these defines (and the ones from DRM) into r300_reg.h and sync up
* with DRM */
+#define CP_PACKET2 (2 << 30)
#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
#define CP_PACKET3( pkt, n ) \
(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
-static INLINE uint32_t cmdpacket0(int reg, int count)
+static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
+ int reg, int count)
{
- drm_r300_cmd_header_t cmd;
-
- cmd.packet0.cmd_type = R300_CMD_PACKET0;
- cmd.packet0.count = count;
- cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
- cmd.packet0.reglo = ((unsigned int)reg & 0x00FF);
-
- return cmd.u;
+ if (!rscrn->driScreen->dri2.enabled) {
+ drm_r300_cmd_header_t cmd;
+
+ cmd.packet0.cmd_type = R300_CMD_PACKET0;
+ cmd.packet0.count = count;
+ cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
+ cmd.packet0.reglo = ((unsigned int)reg & 0x00FF);
+
+ return cmd.u;
+ }
+ if (count) {
+ return CP_PACKET0(reg, count - 1);
+ }
+ return CP_PACKET2;
}
-static INLINE uint32_t cmdvpu(int addr, int count)
+static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count)
{
drm_r300_cmd_header_t cmd;
return cmd.u;
}
-static INLINE uint32_t cmdr500fp(int addr, int count, int type, int clamp)
+static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn,
+ int addr, int count, int type, int clamp)
{
drm_r300_cmd_header_t cmd;
return cmd.u;
}
-static INLINE uint32_t cmdpacket3(int packet)
+static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet)
{
drm_r300_cmd_header_t cmd;
return cmd.u;
}
-static INLINE uint32_t cmdcpdelay(unsigned short count)
+static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
+ unsigned short count)
{
drm_r300_cmd_header_t cmd;
return cmd.u;
}
-static INLINE uint32_t cmdwait(unsigned char flags)
+static INLINE uint32_t cmdwait(struct radeon_screen *rscrn,
+ unsigned char flags)
{
drm_r300_cmd_header_t cmd;
return cmd.u;
}
-static INLINE uint32_t cmdpacify(void)
+static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
{
drm_r300_cmd_header_t cmd;
/** Single register write to command buffer; requires 2 dwords. */
#define OUT_BATCH_REGVAL(reg, val) \
- OUT_BATCH(cmdpacket0((reg), 1)); \
+ OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), 1)); \
OUT_BATCH((val))
/** Continuous register range write to command buffer; requires 1 dword,
* expects count dwords afterwards for register contents. */
#define OUT_BATCH_REGSEQ(reg, count) \
- OUT_BATCH(cmdpacket0((reg), (count)));
+ OUT_BATCH(cmdpacket0(b_l_r300->radeon.radeonScreen, (reg), (count)));
/** Write a 32 bit float to the ring; requires 1 dword. */
#define OUT_BATCH_FLOAT32(f) \
* Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
*/
#define OUT_BATCH_PACKET3(packet, num_extra) do {\
- OUT_BATCH(cmdpacket3(R300_CMD_PACKET3_RAW)); \
+ if (!b_l_r300->radeon.radeonScreen->driScreen->dri2.enabled) { \
+ OUT_BATCH(cmdpacket3(b_l_r300->radeon.radeonScreen,\
+ R300_CMD_PACKET3_RAW)); \
+ }\
OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
} while(0)
{
BATCH_LOCALS(rmesa);
- BEGIN_BATCH(1);
- OUT_BATCH(cmdpacify());
- END_BATCH();
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ BEGIN_BATCH(1);
+ OUT_BATCH(cmdpacify(rmesa->radeon.radeonScreen));
+ END_BATCH();
+ }
}
void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
{
BATCH_LOCALS(rmesa);
- BEGIN_BATCH(1);
- OUT_BATCH(cmdcpdelay(count));
- END_BATCH();
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ BEGIN_BATCH(1);
+ OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
+ END_BATCH();
+ }
}
void static INLINE cp_wait(r300ContextPtr rmesa, unsigned char flags)
{
BATCH_LOCALS(rmesa);
-
- BEGIN_BATCH(1);
- OUT_BATCH(cmdwait(flags));
- END_BATCH();
+ uint32_t wait_until;
+
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ BEGIN_BATCH_NO_AUTOSTATE(1);
+ OUT_BATCH(cmdwait(rmesa->radeon.radeonScreen, flags));
+ END_BATCH();
+ } else {
+ switch(flags) {
+ case R300_WAIT_2D:
+ wait_until = (1 << 14);
+ break;
+ case R300_WAIT_3D:
+ wait_until = (1 << 15);
+ break;
+ case R300_NEW_WAIT_2D_3D:
+ wait_until = (1 << 14) | (1 << 15);
+ break;
+ case R300_NEW_WAIT_2D_2D_CLEAN:
+ wait_until = (1 << 14) | (1 << 16) | (1 << 18);
+ break;
+ case R300_NEW_WAIT_3D_3D_CLEAN:
+ wait_until = (1 << 15) | (1 << 17) | (1 << 18);
+ break;
+ case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
+ wait_until = (1 << 14) | (1 << 16) | (1 << 18);
+ wait_until |= (1 << 15) | (1 << 17) | (1 << 18);
+ break;
+ default:
+ return;
+ }
+ BEGIN_BATCH_NO_AUTOSTATE(2);
+ OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+ OUT_BATCH(wait_until);
+ END_BATCH();
+ }
}
extern int r300EmitArrays(GLcontext * ctx);
#include "radeon_reg.h"
#include "r300_emit.h"
#include "r300_fragprog.h"
+#include "r300_context.h"
#include "vblank.h"
+#define R200_3D_DRAW_IMMD_2 0xC0003500
+
#define CLEARBUFFER_COLOR 0x1
#define CLEARBUFFER_DEPTH 0x2
#define CLEARBUFFER_STENCIL 0x4
dPriv->w, dPriv->h);
if (rrb) {
- cbpitch = rrb->pitch;
+ cbpitch = (rrb->pitch / rrb->cpp);
if (rrb->cpp == 4)
cbpitch |= R300_COLOR_FORMAT_ARGB8888;
else
#if 1
if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) {
assert(rrbd != 0);
- cbpitch = rrbd->pitch;
+ cbpitch = (rrbd->pitch / rrbd->cpp);
if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){
cbpitch |= R300_DEPTHMACROTILE_ENABLE;
}
- if (r300->radeon.glCtx->Visual.depthBits == 24) {
+ if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
cbpitch |= R300_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(4);
END_BATCH();
}
#endif
- BEGIN_BATCH_NO_AUTOSTATE(15);
+ BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(RB3D_COLOR_CHANNEL_MASK, 1);
if (flags & CLEARBUFFER_COLOR) {
OUT_BATCH((ctx->Color.ColorMask[BCOMP] ? RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 : 0) |
OUT_BATCH(0);
}
- OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
{
uint32_t t1, t2;
R300_S_FRONT_ZFAIL_OP_SHIFT);
}
+ OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3);
OUT_BATCH(t1);
OUT_BATCH(t2);
- OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << R300_STENCILWRITEMASK_SHIFT) |
+ OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
+ R300_STENCILWRITEMASK_SHIFT) |
(ctx->Stencil.Clear & R300_STENCILREF_MASK));
+ END_BATCH();
}
- OUT_BATCH(cmdpacket3(R300_CMD_PACKET3_CLEAR));
- OUT_BATCH_FLOAT32(dPriv->w / 2.0);
- OUT_BATCH_FLOAT32(dPriv->h / 2.0);
- OUT_BATCH_FLOAT32(ctx->Depth.Clear);
- OUT_BATCH_FLOAT32(1.0);
- OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
- OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
- OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
- OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
- END_BATCH();
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ BEGIN_BATCH_NO_AUTOSTATE(9);
+ OUT_BATCH(cmdpacket3(r300->radeon.radeonScreen, R300_CMD_PACKET3_CLEAR));
+ OUT_BATCH_FLOAT32(dPriv->w / 2.0);
+ OUT_BATCH_FLOAT32(dPriv->h / 2.0);
+ OUT_BATCH_FLOAT32(ctx->Depth.Clear);
+ OUT_BATCH_FLOAT32(1.0);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
+ END_BATCH();
+ } else {
+ OUT_BATCH(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
+ OUT_BATCH(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
+ (1 << R300_PRIM_NUM_VERTICES_SHIFT));
+ OUT_BATCH_FLOAT32(dPriv->w / 2.0);
+ OUT_BATCH_FLOAT32(dPriv->h / 2.0);
+ OUT_BATCH_FLOAT32(ctx->Depth.Clear);
+ OUT_BATCH_FLOAT32(1.0);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[0]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[1]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[2]);
+ OUT_BATCH_FLOAT32(ctx->Color.ClearColor[3]);
+ }
r300EmitCacheFlush(rmesa);
cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1));
OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0));
- OUT_BATCH(cmdr500fp(0, 1, 0, 0));
+ OUT_BATCH(cmdr500fp(r300->radeon.radeonScreen, 0, 1, 0, 0));
OUT_BATCH(R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
END_BATCH();
if (has_tcl) {
+ struct r300_state_atom vpu;
+ uint32_t _cmd[10];
R300_STATECHANGE(r300, pvs);
R300_STATECHANGE(r300, vpi);
- BEGIN_BATCH(13);
+ BEGIN_BATCH(4);
OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
(0 << R300_PVS_XYZW_VALID_INST_SHIFT) |
OUT_BATCH((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) |
(0 << R300_PVS_MAX_CONST_ADDR_SHIFT));
OUT_BATCH(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
-
- OUT_BATCH(cmdvpu(0, 2));
- OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT));
- OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
- OUT_BATCH(PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
- OUT_BATCH(0x0);
-
- OUT_BATCH(PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, PVS_DST_REG_OUT));
- OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
- OUT_BATCH(PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE));
- OUT_BATCH(0x0);
END_BATCH();
+
+ vpu.check = check_vpu;
+ vpu.cmd = _cmd;
+ vpu.cmd[0] = cmdvpu(r300->radeon.radeonScreen, 0, 2);
+
+ vpu.cmd[1] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE,
+ 0, 0xf, PVS_DST_REG_OUT);
+ vpu.cmd[2] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y,
+ PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W,
+ PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ vpu.cmd[3] = PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ vpu.cmd[4] = 0x0;
+
+ vpu.cmd[5] = PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf,
+ PVS_DST_REG_OUT);
+ vpu.cmd[6] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X,
+ PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z,
+ PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT,
+ VSF_FLAG_NONE);
+ vpu.cmd[7] = PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_SELECT_FORCE_0,
+ PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
+ vpu.cmd[8] = 0x0;
+ emit_vpu(r300, &vpu);
}
}
r300EnsureCmdBufSpace(r300, 421 * 3, __FUNCTION__);
if (flags || bits)
r300EmitClearState(ctx);
- rrbd = (void *)r300->radeon.state.depth_buffer;
+ rrbd = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
if (flags & BUFFER_BIT_FRONT_LEFT) {
rrb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
calculate_miptree_layout(mt);
- mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom, 0, mt->totalsize, 1024, 0);
+ mt->bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ 0, mt->totalsize, 1024,
+ RADEON_GEM_DOMAIN_VRAM,
+ 0);
return mt;
}
rmesa->state.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
0, n_elts * 4, 4,
- RADEON_GEM_DOMAIN_GTT);
+ RADEON_GEM_DOMAIN_GTT, 0);
rmesa->state.elt_dma_offset = 0;
radeon_bo_map(rmesa->state.elt_dma_bo, 1);
out = rmesa->state.elt_dma_bo->ptr + rmesa->state.elt_dma_offset;
type |
R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2);
OUT_BATCH_RELOC(0, rmesa->state.elt_dma_bo,
rmesa->state.elt_dma_offset, 0);
OUT_BATCH(vertex_count);
+ } else {
+ OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
+ OUT_BATCH(R300_EB_UNK1 | (0 << 16) | R300_EB_UNK2);
+ OUT_BATCH(rmesa->state.elt_dma_offset);
+ OUT_BATCH(vertex_count);
+ radeon_cs_write_reloc(rmesa->cmdbuf.cs,
+ rmesa->state.elt_dma_bo,
+ 0,
+ rmesa->state.elt_dma_bo->size,
+ 0);
+ }
END_BATCH();
}
}
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
+
+ if (!rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
for (i = 0; i + 1 < nr; i += 2) {
OUT_BATCH((rmesa->state.aos[i].components << 0) |
(rmesa->state.aos[i].stride << 8) |
OUT_BATCH_RELOC(0, rmesa->state.aos[nr - 1].bo,
rmesa->state.aos[nr - 1].offset + offset * 4 * rmesa->state.aos[nr - 1].stride, 0);
}
+ } else {
+ for (i = 0; i + 1 < nr; i += 2) {
+ OUT_BATCH((rmesa->state.aos[i].components << 0) |
+ (rmesa->state.aos[i].stride << 8) |
+ (rmesa->state.aos[i + 1].components << 16) |
+ (rmesa->state.aos[i + 1].stride << 24));
+
+ voffset = rmesa->state.aos[i + 0].offset +
+ offset * 4 * rmesa->state.aos[i + 0].stride;
+ OUT_BATCH(voffset);
+ voffset = rmesa->state.aos[i + 1].offset +
+ offset * 4 * rmesa->state.aos[i + 1].stride;
+ OUT_BATCH(voffset);
+ }
+
+ if (nr & 1) {
+ OUT_BATCH((rmesa->state.aos[nr - 1].components << 0) |
+ (rmesa->state.aos[nr - 1].stride << 8));
+ OUT_BATCH(rmesa->state.aos[nr - 1].offset + offset * 4 *
+ rmesa->state.aos[nr - 1].stride);
+ }
+ for (i = 0; i + 1 < nr; i += 2) {
+ #if 0
+ fprintf(stderr, "3D_LOAD_VBPNTR 0x%08X & 0x%08X\n",
+ rmesa->state.aos[i+0].bo->handle,
+ rmesa->state.aos[i+1].bo->handle);
+ #endif
+ radeon_cs_write_reloc(rmesa->cmdbuf.cs,
+ rmesa->state.aos[i+0].bo,
+ 0,
+ rmesa->state.aos[i+0].bo->size,
+ 0);
+ radeon_cs_write_reloc(rmesa->cmdbuf.cs,
+ rmesa->state.aos[i+1].bo,
+ 0,
+ rmesa->state.aos[i+1].bo->size,
+ 0);
+ }
+ if (nr & 1) {
+ radeon_cs_write_reloc(rmesa->cmdbuf.cs,
+ rmesa->state.aos[nr-1].bo,
+ 0,
+ rmesa->state.aos[nr-1].bo->size,
+ 0);
+ }
+ }
END_BATCH();
}
static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
GLsizei width, GLsizei height)
{
+ r300ContextPtr rmesa = R300_CONTEXT(ctx);
+ __DRIcontext *driContext = rmesa->radeon.dri.context;
/* Don't pipeline viewport changes, conflict with window offset
* setting below. Could apply deltas to rescue pipelined viewport
* values, or keep the originals hanging around.
*/
+ if (rmesa->radeon.radeonScreen->driScreen->dri2.enabled) {
+ radeon_update_renderbuffers(driContext, driContext->driDrawablePriv);
+ if (driContext->driDrawablePriv != driContext->driReadablePriv) {
+ radeon_update_renderbuffers(driContext,
+ driContext->driReadablePriv);
+ }
+ }
r300UpdateWindow(ctx);
}
assert(rrb->pitch);
R300_STATECHANGE(rmesa, cb);
-
-#if 0
- R200_STATECHANGE(rmesa, ctx);
-
- /* Note: we used the (possibly) page-flipped values */
- rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET]
- = ((drb->flippedOffset + rmesa->r200Screen->fbLocation)
- & R200_COLOROFFSET_MASK);
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = drb->flippedPitch;
-
- if (rmesa->sarea->tiling_enabled) {
- rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |=
- R200_COLOR_TILE_ENABLE;
- }
-#endif
}
static void
}
r300->hw.fpt.cmd[R300_FPT_CMD_0] =
- cmdpacket0(R300_US_TEX_INST_0, code->tex.length);
+ cmdpacket0(r300->radeon.radeonScreen,
+ R300_US_TEX_INST_0, code->tex.length);
}
static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
}
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER0_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, last_hw_tmu + 1);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER1_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, last_hw_tmu + 1);
r300->hw.tex.size.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_SIZE_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, last_hw_tmu + 1);
r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FORMAT_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, last_hw_tmu + 1);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FORMAT2_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, last_hw_tmu + 1);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_OFFSET_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, last_hw_tmu + 1);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, last_hw_tmu + 1);
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, last_hw_tmu + 1);
if (!fp) /* should only happenen once, just after context is created */
return;
r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
- cmdpacket0(R300_TX_FILTER0_0, 1);
+ cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 1);
}
r300SetupFragmentShaderTextures(ctx, tmu_mappings);
} else
| R300_HIRES_EN;
assert(high_rr >= 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R300_RS_INST_0, high_rr + 1);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, high_rr + 1);
r300->hw.rc.cmd[2] = high_rr;
if (InputsRead)
| R300_HIRES_EN;
assert(high_rr >= 0);
- r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(R500_RS_INST_0, high_rr + 1);
+ r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, high_rr + 1);
r300->hw.rc.cmd[2] = 0xC0 | high_rr;
if (InputsRead)
(inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
}
+
static void r300SetupVertexProgram(r300ContextPtr rmesa)
{
GLcontext *ctx = rmesa->radeon.glCtx;
static void r300ResetHwState(r300ContextPtr r300)
{
GLcontext *ctx = r300->radeon.glCtx;
+ struct radeon_renderbuffer *rrb;
int has_tcl = 1;
if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
-
- if (r300->radeon.sarea->tiling_enabled) {
+ rrb = r300->radeon.state.depth_buffer;
+ if (rrb && rrb->bo && (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)) {
/* XXX: Turn off when clearing buffers ? */
r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE;
R300_STATECHANGE(rmesa, fpi[1]);
R300_STATECHANGE(rmesa, fpi[2]);
R300_STATECHANGE(rmesa, fpi[3]);
- rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_INST_0, code->alu.length);
- rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_RGB_ADDR_0, code->alu.length);
- rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_INST_0, code->alu.length);
- rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
+ rmesa->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, code->alu.length);
+ rmesa->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, code->alu.length);
+ rmesa->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, code->alu.length);
+ rmesa->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0;
rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1;
}
R300_STATECHANGE(rmesa, fpp);
- rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(R300_PFS_PARAM_0_X, code->const_nr * 4);
+ rmesa->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(rmesa->radeon.radeonScreen, R300_PFS_PARAM_0_X, code->const_nr * 4);
for (i = 0; i < code->const_nr; i++) {
const GLfloat *constant = get_fragmentprogram_constant(ctx,
&fp->mesa_program.Base, code->constant[i]);
GLuint bytes = vsize * nverts;
rmesa->swtcl.bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
- 0, bytes, 4, RADEON_GEM_DOMAIN_GTT);
+ 0, bytes, 4, RADEON_GEM_DOMAIN_GTT, 0);
radeon_bo_map(rmesa->swtcl.bo, 1);
if (rmesa->swtcl.flush == NULL) {
rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
ctx = radeon->glCtx;
if (ctx->Visual.doubleBufferMode) {
- _mesa_notifySwapBuffers(ctx); /* flush pending rendering comands */
+ _mesa_notifySwapBuffers(ctx);/* flush pending rendering comands */
if (radeon->doPageFlip) {
radeonPageFlip(dPriv);
} else {
radeon->radeonScreen->fbLocation,
size,
4096,
+ RADEON_GEM_DOMAIN_VRAM,
0);
}
rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->frontPitch;
+ rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
}
if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
if (!rb->bo) {
radeon->radeonScreen->fbLocation,
size,
4096,
+ RADEON_GEM_DOMAIN_VRAM,
0);
}
rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->backPitch;
+ rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
}
if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
if (!rb->bo) {
radeon->radeonScreen->fbLocation,
size,
4096,
+ RADEON_GEM_DOMAIN_VRAM,
0);
}
rb->cpp = radeon->radeonScreen->cpp;
- rb->pitch = radeon->radeonScreen->depthPitch;
+ rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
}
}
+void
+radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
+{
+ unsigned int attachments[10];
+ __DRIbuffer *buffers;
+ __DRIscreen *screen;
+ struct radeon_renderbuffer *rb;
+ int i, count;
+ GLframebuffer *draw;
+ radeonContextPtr radeon;
+
+ draw = drawable->driverPrivate;
+ screen = context->driScreenPriv;
+ radeon = (radeonContextPtr) context->driverPrivate;
+ i = 0;
+ if ((rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_BACK_LEFT;
+ }
+ if ((rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer)) {
+ attachments[i++] = __DRI_BUFFER_DEPTH;
+ }
+
+ buffers = (*screen->dri2.loader->getBuffers)(drawable,
+ &drawable->w,
+ &drawable->h,
+ attachments, i,
+ &count,
+ drawable->loaderPrivate);
+ if (buffers == NULL)
+ return;
+
+ /* set one cliprect to cover the whole drawable */
+ drawable->x = 0;
+ drawable->y = 0;
+ drawable->backX = 0;
+ drawable->backY = 0;
+ drawable->numClipRects = 1;
+ drawable->pClipRects[0].x1 = 0;
+ drawable->pClipRects[0].y1 = 0;
+ drawable->pClipRects[0].x2 = drawable->w;
+ drawable->pClipRects[0].y2 = drawable->h;
+ drawable->numBackClipRects = 1;
+ drawable->pBackClipRects[0].x1 = 0;
+ drawable->pBackClipRects[0].y1 = 0;
+ drawable->pBackClipRects[0].x2 = drawable->w;
+ drawable->pBackClipRects[0].y2 = drawable->h;
+ for (i = 0; i < count; i++) {
+ switch (buffers[i].attachment) {
+ case __DRI_BUFFER_FRONT_LEFT:
+ rb = (void *)draw->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ if (rb->bo == NULL) {
+ fprintf(stderr, "failled to attach front %d\n",
+ buffers[i].name);
+ }
+ break;
+ case __DRI_BUFFER_BACK_LEFT:
+ rb = (void *)draw->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ break;
+ case __DRI_BUFFER_DEPTH:
+ rb = (void *)draw->Attachment[BUFFER_DEPTH].Renderbuffer;
+ rb->cpp = buffers[i].cpp;
+ rb->pitch = buffers[i].pitch;
+ rb->height = drawable->h;
+ rb->has_surface = 0;
+ rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
+ buffers[i].name,
+ 0,
+ 0,
+ RADEON_GEM_DOMAIN_VRAM,
+ buffers[i].flags);
+ break;
+ case __DRI_BUFFER_STENCIL:
+ break;
+ case __DRI_BUFFER_ACCUM:
+ default:
+ fprintf(stderr,
+ "unhandled buffer attach event, attacment type %d\n",
+ buffers[i].attachment);
+ return;
+ }
+ }
+ radeon = (radeonContextPtr) context->driverPrivate;
+ driUpdateFramebufferSize(radeon->glCtx, drawable);
+}
+
/* Force the context `c' to be the current context and associate with it
* buffer `b'.
_mesa_make_current(NULL, NULL, NULL);
return GL_TRUE;
}
-
radeon = (radeonContextPtr) driContextPriv->driverPrivate;
dfb = driDrawPriv->driverPrivate;
rfb = driReadPriv->driverPrivate;
+ if (driContextPriv->driScreenPriv->dri2.enabled) {
+ radeon_update_renderbuffers(driContextPriv, driDrawPriv);
+ if (driDrawPriv != driReadPriv)
+ radeon_update_renderbuffers(driContextPriv, driReadPriv);
+ radeon->state.color.rrb =
+ (void *)dfb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
+ radeon->state.depth_buffer =
+ (void *)dfb->Attachment[BUFFER_DEPTH].Renderbuffer;
+ }
+
+
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s ctx %p\n", __FUNCTION__, radeon->glCtx);
if (driReadPriv != driDrawPriv)
driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
- radeon_make_renderbuffer_current(radeon, dfb);
+ if (!driContextPriv->driScreenPriv->dri2.enabled) {
+ radeon_make_renderbuffer_current(radeon, dfb);
+ }
_mesa_make_current(radeon->glCtx, dfb, rfb);
_mesa_update_state(radeon->glCtx);
- radeonUpdatePageFlipping(radeon);
+ if (!driContextPriv->driScreenPriv->dri2.enabled) {
+ radeonUpdatePageFlipping(radeon);
+ }
if (RADEON_DEBUG & DEBUG_DRI)
fprintf(stderr, "End %s\n", __FUNCTION__);
__DRIdrawablePrivate * driDrawPriv,
__DRIdrawablePrivate * driReadPriv);
extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
+void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
/* ================================================================
* Debugging:
do { \
char __ret = 0; \
DEBUG_CHECK_LOCK(); \
+ if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \
DRM_CAS((rmesa)->dri.hwLock, (rmesa)->dri.hwContext, \
(DRM_LOCK_HELD | (rmesa)->dri.hwContext), __ret); \
if (__ret) \
radeonGetLock((rmesa), 0); \
+ }\
DEBUG_LOCK(); \
} while (0)
#define UNLOCK_HARDWARE( rmesa ) \
do { \
+ if (!(rmesa)->radeonScreen->driScreen->dri2.enabled) { \
DRM_UNLOCK((rmesa)->dri.fd, \
(rmesa)->dri.hwLock, \
(rmesa)->dri.hwContext); \
DEBUG_RESET(); \
+ }\
} while (0)
#endif /* __RADEON_LOCK_H__ */
struct radeon_renderbuffer *rrb = (void *) rb; \
const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
const GLuint bottom = dPriv->h - 1; \
- GLubyte *buf = (GLubyte *) ((char*)rrb->bo->ptr) \
- + (dPriv->y * rrb->pitch + dPriv->x) * rrb->cpp; \
GLuint p; \
(void)p;
const __DRIdrawablePrivate *dPriv = rrb->dPriv; \
const GLuint bottom = dPriv->h - 1; \
GLuint xo = dPriv->x; \
- GLuint yo = dPriv->y; \
- GLubyte *buf = (GLubyte *) rrb->bo->ptr;
+ GLuint yo = dPriv->y;
#define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
#define HW_UNLOCK()
+static GLubyte *radeon_ptr32(const struct radeon_renderbuffer * rrb,
+ GLint x, GLint y)
+{
+ GLubyte *ptr = rrb->bo->ptr;
+ uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
+ GLint offset;
+ GLint nmacroblkpl;
+ GLint nmicroblkpl;
+
+ if (rrb->has_surface || !(rrb->bo->flags & mask)) {
+ offset = x * rrb->cpp + y * rrb->pitch;
+ } else {
+ offset = 0;
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) {
+ nmacroblkpl = rrb->pitch >> 5;
+ offset += ((y >> 4) * nmacroblkpl) << 11;
+ offset += ((y & 15) >> 1) << 8;
+ offset += (y & 1) << 4;
+ offset += (x >> 5) << 11;
+ offset += ((x & 31) >> 2) << 5;
+ offset += (x & 3) << 2;
+ } else {
+ nmacroblkpl = rrb->pitch >> 6;
+ offset += ((y >> 3) * nmacroblkpl) << 11;
+ offset += (y & 7) << 8;
+ offset += (x >> 6) << 11;
+ offset += ((x & 63) >> 3) << 5;
+ offset += (x & 7) << 2;
+ }
+ } else {
+ nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5;
+ offset += (y * nmicroblkpl) << 5;
+ offset += (x >> 3) << 5;
+ offset += (x & 7) << 2;
+ }
+ }
+ return &ptr[offset];
+}
+
+static GLubyte *radeon_ptr16(const struct radeon_renderbuffer * rrb,
+ GLint x, GLint y)
+{
+ GLubyte *ptr = rrb->bo->ptr;
+ uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
+ GLint offset;
+ GLint nmacroblkpl;
+ GLint nmicroblkpl;
+
+ if (rrb->has_surface || !(rrb->bo->flags & mask)) {
+ offset = x * rrb->cpp + y * rrb->pitch;
+ } else {
+ offset = 0;
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) {
+ nmacroblkpl = rrb->pitch >> 6;
+ offset += ((y >> 4) * nmacroblkpl) << 11;
+ offset += ((y & 15) >> 1) << 8;
+ offset += (y & 1) << 4;
+ offset += (x >> 6) << 11;
+ offset += ((x & 63) >> 3) << 5;
+ offset += (x & 7) << 1;
+ } else {
+ nmacroblkpl = rrb->pitch >> 7;
+ offset += ((y >> 3) * nmacroblkpl) << 11;
+ offset += (y & 7) << 8;
+ offset += (x >> 7) << 11;
+ offset += ((x & 127) >> 4) << 5;
+ offset += (x & 15) << 2;
+ }
+ } else {
+ nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5;
+ offset += (y * nmicroblkpl) << 5;
+ offset += (x >> 4) << 5;
+ offset += (x & 15) << 2;
+ }
+ }
+ return &ptr[offset];
+}
+
+static GLubyte *radeon_ptr(const struct radeon_renderbuffer * rrb,
+ GLint x, GLint y)
+{
+ GLubyte *ptr = rrb->bo->ptr;
+ uint32_t mask = RADEON_BO_FLAGS_MACRO_TILE | RADEON_BO_FLAGS_MICRO_TILE;
+ GLint offset;
+ GLint microblkxs;
+ GLint macroblkxs;
+ GLint nmacroblkpl;
+ GLint nmicroblkpl;
+
+ if (rrb->has_surface || !(rrb->bo->flags & mask)) {
+ offset = x * rrb->cpp + y * rrb->pitch;
+ } else {
+ offset = 0;
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
+ if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) {
+ microblkxs = 16 / rrb->cpp;
+ macroblkxs = 128 / rrb->cpp;
+ nmacroblkpl = rrb->pitch / macroblkxs;
+ offset += ((y >> 4) * nmacroblkpl) << 11;
+ offset += ((y & 15) >> 1) << 8;
+ offset += (y & 1) << 4;
+ offset += (x / macroblkxs) << 11;
+ offset += ((x & (macroblkxs - 1)) / microblkxs) << 5;
+ offset += (x & (microblkxs - 1)) * rrb->cpp;
+ } else {
+ microblkxs = 32 / rrb->cpp;
+ macroblkxs = 256 / rrb->cpp;
+ nmacroblkpl = rrb->pitch / macroblkxs;
+ offset += ((y >> 3) * nmacroblkpl) << 11;
+ offset += (y & 7) << 8;
+ offset += (x / macroblkxs) << 11;
+ offset += ((x & (macroblkxs - 1)) / microblkxs) << 5;
+ offset += (x & (microblkxs - 1)) * rrb->cpp;
+ }
+ } else {
+ microblkxs = 32 / rrb->cpp;
+ nmicroblkpl = ((rrb->pitch + 31) & ~31) >> 5;
+ offset += (y * nmicroblkpl) << 5;
+ offset += (x / microblkxs) << 5;
+ offset += (x & (microblkxs - 1)) * rrb->cpp;
+ }
+ }
+ return &ptr[offset];
+}
+
/* ================================================================
* Color buffer
*/
#define TAG(x) radeon##x##_RGB565
#define TAG2(x,y) radeon##x##_RGB565##y
-#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 2)
+#define GET_PTR(X,Y) radeon_ptr16(rrb, (X), (Y))
#include "spantmp2.h"
/* 32 bit, ARGB8888 color spanline and pixel functions
#define TAG(x) radeon##x##_ARGB8888
#define TAG2(x,y) radeon##x##_ARGB8888##y
-#define GET_PTR(X,Y) (buf + ((Y) * rrb->pitch + (X)) * 4)
+#define GET_PTR(X,Y) radeon_ptr32(rrb, (X), (Y))
#include "spantmp2.h"
/* ================================================================
* too...
*/
-static GLuint radeon_mba_z32(const struct radeon_renderbuffer * rrb,
- GLint x, GLint y)
-{
- GLuint pitch = rrb->pitch;
- if (rrb->depthHasSurface) {
- return 4 * (x + y * pitch);
- } else {
- GLuint ba, address = 0; /* a[0..1] = 0 */
-
-#ifdef COMPILE_R300
- ba = (y / 8) * (pitch / 8) + (x / 8);
-#else
- ba = (y / 16) * (pitch / 16) + (x / 16);
-#endif
-
- address |= (x & 0x7) << 2; /* a[2..4] = x[0..2] */
- address |= (y & 0x3) << 5; /* a[5..6] = y[0..1] */
- address |= (((x & 0x10) >> 2) ^ (y & 0x4)) << 5; /* a[7] = x[4] ^ y[2] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
-
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |= (((x & 0x8) << 1) ^ (y & 0x10)) << 7; /* a[11] = x[3] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
-}
-
-static INLINE GLuint
-radeon_mba_z16(const struct radeon_renderbuffer *rrb, GLint x, GLint y)
-{
- GLuint pitch = rrb->pitch;
- if (rrb->depthHasSurface) {
- return 2 * (x + y * pitch);
- } else {
- GLuint ba, address = 0; /* a[0] = 0 */
-
- ba = (y / 16) * (pitch / 32) + (x / 32);
-
- address |= (x & 0x7) << 1; /* a[1..3] = x[0..2] */
- address |= (y & 0x7) << 4; /* a[4..6] = y[0..2] */
- address |= (x & 0x8) << 4; /* a[7] = x[3] */
- address |= (ba & 0x3) << 8; /* a[8..9] = ba[0..1] */
- address |= (y & 0x8) << 7; /* a[10] = y[3] */
- address |= ((x & 0x10) ^ (y & 0x10)) << 7; /* a[11] = x[4] ^ y[4] */
- address |= (ba & ~0x3) << 10; /* a[12..] = ba[2..] */
-
- return address;
- }
-}
-
/* 16-bit depth buffer functions
*/
#define VALUE_TYPE GLushort
#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo )) = d;
+ *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo) = d
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)(buf + radeon_mba_z16( rrb, _x + xo, _y + yo ));
+ d = *(GLushort *)radeon_ptr(rrb, _x + xo, _y + yo)
#define TAG(x) radeon##x##_z16
#include "depthtmp.h"
#ifdef COMPILE_R300
#define WRITE_DEPTH( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \
+ GLuint tmp = *_ptr; \
tmp &= 0x000000ff; \
tmp |= ((d << 8) & 0xffffff00); \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#else
#define WRITE_DEPTH( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \
+ GLuint tmp = *_ptr; \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#endif
#ifdef COMPILE_R300
#define READ_DEPTH( d, _x, _y ) \
do { \
- d = (*(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \
- _y + yo )) & 0xffffff00) >> 8; \
+ d = (*(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo)) & 0xffffff00) >> 8; \
}while(0)
#else
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLuint *)(buf + radeon_mba_z32( rrb, _x + xo, \
- _y + yo )) & 0x00ffffff;
+ d = *(GLuint*)(radeon_ptr32(rrb, _x + xo, _y + yo )) & 0x00ffffff;
#endif
-
+/*
+ fprintf(stderr, "dval(%d, %d, %d, %d)=0x%08X\n", _x, xo, _y, yo, d);\
+ d = *(GLuint*)(radeon_ptr(rrb, _x + xo, _y + yo )) & 0x00ffffff;
+*/
#define TAG(x) radeon##x##_z24_s8
#include "depthtmp.h"
#ifdef COMPILE_R300
#define WRITE_STENCIL( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
+ GLuint tmp = *_ptr; \
tmp &= 0xffffff00; \
tmp |= (d) & 0xff; \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#else
#define WRITE_STENCIL( _x, _y, d ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32(rrb, _x + xo, _y + yo); \
+ GLuint tmp = *_ptr; \
tmp &= 0x00ffffff; \
tmp |= (((d) & 0xff) << 24); \
- *(GLuint *)(buf + offset) = tmp; \
+ *_ptr = tmp; \
} while (0)
#endif
#ifdef COMPILE_R300
#define READ_STENCIL( d, _x, _y ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \
+ GLuint tmp = *_ptr; \
d = tmp & 0x000000ff; \
} while (0)
#else
#define READ_STENCIL( d, _x, _y ) \
do { \
- GLuint offset = radeon_mba_z32( rrb, _x + xo, _y + yo ); \
- GLuint tmp = *(GLuint *)(buf + offset); \
+ GLuint *_ptr = (GLuint*)radeon_ptr32( rrb, _x + xo, _y + yo ); \
+ GLuint tmp = *_ptr; \
d = (tmp & 0xff000000) >> 24; \
} while (0)
#endif
static void map_buffer(struct gl_renderbuffer *rb, GLboolean write)
{
struct radeon_renderbuffer *rrb = (void*)rb;
+ int r;
if (rrb->bo) {
- radeon_bo_map(rrb->bo, write);
+ r = radeon_bo_map(rrb->bo, write);
+ if (r) {
+ fprintf(stderr, "(%s) error(%d) mapping buffer.\n",
+ __FUNCTION__, r);
+ }
}
}
GLframebuffer *const draw_fb = (GLframebuffer*)drawable->driverPrivate;
GLframebuffer *const read_fb = (GLframebuffer*)readable->driverPrivate;
+ if (!radeon->radeonScreen->driScreen->dri2.enabled) {
if (draw_fb->_ColorDrawBufferIndexes[0] == BUFFER_BACK_LEFT) {
/* Can't ignore 2d windows if we are page flipping. */
if (drawable->numBackClipRects == 0 || radeon->doPageFlip ||
radeon->numClipRects = drawable->numClipRects;
radeon->pClipRects = drawable->pClipRects;
}
+ }
if ((draw_fb->Width != drawable->w) ||
(draw_fb->Height != drawable->h)) {
static struct bo_legacy *bo_allocate(struct bo_manager_legacy *boml,
uint32_t size,
uint32_t alignment,
+ uint32_t domains,
uint32_t flags)
{
struct bo_legacy *bo_legacy;
bo_legacy->base.handle = 0;
bo_legacy->base.size = size;
bo_legacy->base.alignment = alignment;
+ bo_legacy->base.domains = domains;
bo_legacy->base.flags = flags;
bo_legacy->base.ptr = NULL;
bo_legacy->map_count = 0;
}
if (!bo_legacy->static_bo) {
legacy_free_handle(boml, bo_legacy->base.handle);
- if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) {
+ if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) {
/* dma buffers */
bo_dma_free(&bo_legacy->base);
} else {
uint32_t handle,
uint32_t size,
uint32_t alignment,
+ uint32_t domains,
uint32_t flags)
{
struct bo_manager_legacy *boml = (struct bo_manager_legacy *)bom;
return NULL;
}
- bo_legacy = bo_allocate(boml, size, alignment, flags);
+ bo_legacy = bo_allocate(boml, size, alignment, domains, flags);
bo_legacy->static_bo = 0;
r = legacy_new_handle(boml, &bo_legacy->base.handle);
if (r) {
bo_free(bo_legacy);
return NULL;
}
- if (bo_legacy->base.flags & RADEON_GEM_DOMAIN_GTT) {
+ if (bo_legacy->base.domains & RADEON_GEM_DOMAIN_GTT) {
legacy_track_pending(boml);
/* dma buffers */
r = bo_dma_alloc(&(bo_legacy->base));
*eoffset = bo_legacy->offset + bo->size;
return 0;
}
- if (!(bo->flags & RADEON_GEM_DOMAIN_GTT)) {
+ if (!(bo->domains & RADEON_GEM_DOMAIN_GTT)) {
r = bo_vram_validate(bo, soffset, eoffset);
if (r) {
return r;
/* biggest framebuffer size */
size = 4096*4096*4;
/* allocate front */
- bo = bo_allocate(bom, size, 0, 0);
+ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
if (bo == NULL) {
radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
return NULL;
bom->nhandle = bo->base.handle + 1;
}
/* allocate back */
- bo = bo_allocate(bom, size, 0, 0);
+ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
if (bo == NULL) {
radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
return NULL;
bom->nhandle = bo->base.handle + 1;
}
/* allocate depth */
- bo = bo_allocate(bom, size, 0, 0);
+ bo = bo_allocate(bom, size, 0, RADEON_GEM_DOMAIN_VRAM, 0);
if (bo == NULL) {
radeon_bo_manager_legacy_shutdown((struct radeon_bo_manager*)bom);
return NULL;
}
bo->base.flags = 0;
if (scrn->sarea->tiling_enabled) {
- bo->base.flags = RADEON_BO_FLAGS_MACRO_TILE;
+ bo->base.flags |= RADEON_BO_FLAGS_MACRO_TILE;
+ bo->base.flags |= RADEON_BO_FLAGS_MICRO_TILE;
}
bo->static_bo = 1;
bo->offset = bom->screen->depthOffset + bom->fb_location;
{
struct bo_legacy *bo_legacy = (struct bo_legacy*)bo;
- if (bo_legacy->static_bo || (bo->flags & RADEON_GEM_DOMAIN_GTT)) {
+ if (bo_legacy->static_bo || (bo->domains & RADEON_GEM_DOMAIN_GTT)) {
return 0;
}
return bo->size;
unsigned int height;
/* boo Xorg 6.8.2 compat */
- int depthHasSurface;
+ int has_surface;
+
__DRIdrawablePrivate *dPriv;
};
int r;
/* please flush pipe do all pending work */
- cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_SC_SCREENDOOR, 1));
cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(R300_SC_SCREENDOOR, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_SC_SCREENDOOR, 1));
cs_write_dword(cs, 0x00FFFFFF);
- cs_write_dword(cs, cmdpacket0(R300_SC_HYPERZ, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_SC_HYPERZ, 1));
cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(R300_US_CONFIG, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_US_CONFIG, 1));
cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdpacket0(R300_ZB_CNTL, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_ZB_CNTL, 1));
cs_write_dword(cs, 0x0);
- cs_write_dword(cs, cmdwait(R300_WAIT_3D));
- cs_write_dword(cs, cmdpacket0(R300_RB3D_DSTCACHE_CTLSTAT, 1));
+ cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen, R300_WAIT_3D));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_RB3D_DSTCACHE_CTLSTAT, 1));
cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
- cs_write_dword(cs, cmdpacket0(R300_ZB_ZCACHE_CTLSTAT, 1));
+ cs_write_dword(cs, cmdpacket0(csm->ctx->radeonScreen,
+ R300_ZB_ZCACHE_CTLSTAT, 1));
cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
- cs_write_dword(cs, cmdwait(R300_WAIT_3D | R300_WAIT_3D_CLEAN));
+ cs_write_dword(cs, cmdwait(csm->ctx->radeonScreen,
+ R300_WAIT_3D | R300_WAIT_3D_CLEAN));
/* append buffer age */
age.scratch.cmd_type = R300_CMD_SCRATCH;
}
r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
+ if (r) {
+ return r;
+ }
cs_set_age(cs);
- return r;
+ for (int i = 0; i < cs->cdw; i++) {
+ fprintf(stderr, "pkt[%04d]=0x%08X\n", i, cs->packets[i]);
+ }
+ exit(0);
+ return 0;
}
static int cs_destroy(struct radeon_cs *cs)
csm->pending_age = 1;
return (struct radeon_cs_manager*)csm;
}
+
+void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm)
+{
+ free(csm);
+}
#include "radeon_context.h"
struct radeon_cs_manager *radeon_cs_manager_legacy(struct radeon_context *ctx);
+void radeon_cs_manager_legacy_shutdown(struct radeon_cs_manager *csm);
#endif
*/
#include "xmlpool.h"
#include "radeon_bo_legacy.h"
+#include "radeon_bo_gem.h"
#if !RADEON_COMMON /* R100 */
PUBLIC const char __driConfigOptions[] =
return screen;
}
-/* Destroy the device specific screen private data struct.
- */
-static void
-radeonDestroyScreen( __DRIscreenPrivate *sPriv )
+static radeonScreenPtr
+radeonCreateScreen2(__DRIscreenPrivate *sPriv)
{
- radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
+ radeonScreenPtr screen;
+ int i;
+
+ /* Allocate the private area */
+ screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
+ if ( !screen ) {
+ __driUtilMessage("%s: Could not allocate memory for screen structure",
+ __FUNCTION__);
+ fprintf(stderr, "leaving here\n");
+ return NULL;
+ }
+
+#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+ RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
+#endif
+
+ /* parse information in __driConfigOptions */
+ driParseOptionInfo (&screen->optionCache,
+ __driConfigOptions, __driNConfigOptions);
+
+ screen->chip_flags = 0;
+ /* FIXME: do either an ioctl (bad) or a sysfs file for driver to
+ * information about which chipset is their */
+ screen->chip_family = CHIP_FAMILY_RV350;
+ screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300;
- if (!screen)
- return;
+ i = 0;
+ screen->extensions[i++] = &driCopySubBufferExtension.base;
+ screen->extensions[i++] = &driFrameTrackingExtension.base;
+ screen->extensions[i++] = &driReadDrawableExtension;
+
+ if ( screen->irq != 0 ) {
+ screen->extensions[i++] = &driSwapControlExtension.base;
+ screen->extensions[i++] = &driMediaStreamCounterExtension.base;
+ }
+
+#if !RADEON_COMMON
+ screen->extensions[i++] = &radeonTexOffsetExtension.base;
+#endif
- radeon_bo_manager_legacy_shutdown(screen->bom);
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+ if (IS_R200_CLASS(screen))
+ screen->extensions[i++] = &r200AllocateExtension.base;
+
+ screen->extensions[i++] = &r200texOffsetExtension.base;
+#endif
+
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
+ //screen->extensions[i++] = &r300texOffsetExtension.base;
+#endif
+
+ screen->extensions[i++] = NULL;
+ sPriv->extensions = screen->extensions;
- if ( screen->gartTextures.map ) {
- drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
+ screen->driScreen = sPriv;
+ screen->bom = radeon_bo_manager_gem(sPriv->fd);
+ if (screen->bom == NULL) {
+ free(screen);
+ return NULL;
}
- drmUnmapBufs( screen->buffers );
- drmUnmap( screen->status.map, screen->status.size );
- drmUnmap( screen->mmio.map, screen->mmio.size );
+ return screen;
+}
- /* free all option information */
- driDestroyOptionInfo (&screen->optionCache);
+/* Destroy the device specific screen private data struct.
+ */
+static void
+radeonDestroyScreen( __DRIscreenPrivate *sPriv )
+{
+ radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
+
+ if (!screen)
+ return;
+
+ if (sPriv->dri2.enabled) {
+ radeon_bo_manager_gem_shutdown(screen->bom);
+ } else {
+ radeon_bo_manager_legacy_shutdown(screen->bom);
+
+ if ( screen->gartTextures.map ) {
+ drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
+ }
+ drmUnmapBufs( screen->buffers );
+ drmUnmap( screen->status.map, screen->status.size );
+ drmUnmap( screen->mmio.map, screen->mmio.size );
+ }
+
+ /* free all option information */
+ driDestroyOptionInfo (&screen->optionCache);
- FREE( screen );
- sPriv->private = NULL;
+ FREE( screen );
+ sPriv->private = NULL;
}
static GLboolean
radeonInitDriver( __DRIscreenPrivate *sPriv )
{
- sPriv->private = (void *) radeonCreateScreen( sPriv );
- if ( !sPriv->private ) {
- radeonDestroyScreen( sPriv );
- return GL_FALSE;
- }
+ if (sPriv->dri2.enabled) {
+ sPriv->private = (void *) radeonCreateScreen2( sPriv );
+ } else {
+ sPriv->private = (void *) radeonCreateScreen( sPriv );
+ }
+ if ( !sPriv->private ) {
+ radeonDestroyScreen( sPriv );
+ return GL_FALSE;
+ }
- return GL_TRUE;
+ return GL_TRUE;
}
#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
struct radeon_renderbuffer *front =
radeon_create_renderbuffer(rgbFormat, driDrawPriv);
_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
+ front->has_surface = 1;
}
/* back color renderbuffer */
struct radeon_renderbuffer *back =
radeon_create_renderbuffer(rgbFormat, driDrawPriv);
_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
+ back->has_surface = 1;
}
/* depth renderbuffer */
struct radeon_renderbuffer *depth =
radeon_create_renderbuffer(depthFormat, driDrawPriv);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
- depth->depthHasSurface = screen->depthHasSurface;
+ depth->has_surface = screen->depthHasSurface;
}
/* stencil renderbuffer */
struct radeon_renderbuffer *stencil =
radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
- stencil->depthHasSurface = screen->depthHasSurface;
+ stencil->has_surface = screen->depthHasSurface;
}
_mesa_add_soft_renderbuffers(fb,
driDrawPriv);
radeonSetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- depthRb->depthHasSurface = screen->depthHasSurface;
+ depthRb->has_surface = screen->depthHasSurface;
}
else if (mesaVis->depthBits == 24) {
driRenderbuffer *depthRb
driDrawPriv);
radeonSetSpanFunctions(depthRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
- depthRb->depthHasSurface = screen->depthHasSurface;
+ depthRb->has_surface = screen->depthHasSurface;
}
/* stencil renderbuffer */
driDrawPriv);
radeonSetSpanFunctions(stencilRb, mesaVis);
_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
- stencilRb->depthHasSurface = screen->depthHasSurface;
+ stencilRb->has_surface = screen->depthHasSurface;
}
_mesa_add_soft_renderbuffers(fb,
(dri_priv->bpp == 16) ? 0 : 8, 1);
}
+/**
+ * This is the driver specific part of the createNewScreen entry point.
+ * Called when using DRI2.
+ *
+ * \return the __GLcontextModes supported by this driver
+ */
+static const
+__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
+{
+ fprintf(stderr, "DRI2 initialization\n");
+
+ /* Calling driInitExtensions here, with a NULL context pointer,
+ * does not actually enable the extensions. It just makes sure
+ * that all the dispatch offsets for all the extensions that
+ * *might* be enables are known. This is needed because the
+ * dispatch offsets need to be known when _mesa_context_create
+ * is called, but we can't enable the extensions until we have a
+ * context pointer.
+ *
+ * Hello chicken. Hello egg. How are you two today?
+ */
+ driInitExtensions( NULL, card_extensions, GL_FALSE );
+#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
+ driInitExtensions( NULL, blend_extensions, GL_FALSE );
+ driInitSingleExtension( NULL, ARB_vp_extension );
+ driInitSingleExtension( NULL, NV_vp_extension );
+ driInitSingleExtension( NULL, ATI_fs_extension );
+ driInitExtensions( NULL, point_extensions, GL_FALSE );
+#endif
+
+ if (!radeonInitDriver(psp)) {
+ return NULL;
+ }
+
+ fprintf(stderr, "DRI2 initialized\n");
+
+ /* for now fill in all modes */
+ return radeonFillInModes( psp, 24, 24, 8, 1);
+}
/**
* Get information about previous buffer swaps.
.WaitForSBC = NULL,
.SwapBuffersMSC = NULL,
.CopySubBuffer = radeonCopySubBuffer,
+ /* DRI2 */
+ .InitScreen2 = radeonInitScreen2,
};
#else
const struct __DriverAPIRec driDriverAPI = {
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