Add -assert

diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index b602b74d7c3daa5c12491e8093a186b44044c6ce..3bb3a8eb0e455c487b23e4b334dd841e5636353c 100644 (file)
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module