now ignore init attributes on non-register wires in sat command

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 87bff4c484e288a01b238c11ee0cbd54a17a8d5f..a9a00d8a27038bc3607fbceb09d528c58fbf6e6d 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -103,10 +103,30 @@ struct SatHelper
                        RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
                        log_assert(lhs.width == rhs.width);
 
-                       log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
-                       big_lhs.remove2(lhs, &big_rhs);
-                       big_lhs.append(lhs);
-                       big_rhs.append(rhs);
+                       RTLIL::SigSpec removed_bits;
+                       for (int i = 0; i < lhs.width; i++) {
+                               RTLIL::SigSpec bit = lhs.extract(i, 1);
+                               if (!satgen.initial_state.check_all(bit)) {
+                                       removed_bits.append(bit);
+                                       lhs.remove(i, 1);
+                                       rhs.remove(i, 1);
+                                       i--;
+                               }
+                       }
+
+                       lhs.optimize();
+                       rhs.optimize();
+                       removed_bits.optimize();
+
+                       if (removed_bits.width)
+                               log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
+
+                       if (lhs.width) {
+                               log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
+                               big_lhs.remove2(lhs, &big_rhs);
+                               big_lhs.append(lhs);
+                               big_rhs.append(rhs);
+                       }
                }
 
                for (auto &s : sets_init)

diff --git a/tests/sat/initval.v b/tests/sat/initval.v
new file mode 100644 (file)
index 0000000..5b661f8
--- /dev/null
+++ b/tests/sat/initval.v
@@ -0,0 +1,15 @@
+module test(input clk, input [3:0] bar, output [3:0] foo);
+  reg [3:0] foo = 0;
+  reg [3:0] last_bar = 0;
+
+  always @*
+    foo[1:0] <= bar[1:0];
+
+  always @(posedge clk)
+    foo[3:2] <= bar[3:2];
+
+  always @(posedge clk)
+    last_bar <= bar;
+
+  assert property (foo == {last_bar[3:2], bar[1:0]});
+endmodule

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
new file mode 100644 (file)
index 0000000..2079d2f
--- /dev/null
+++ b/tests/sat/initval.ys
@@ -0,0 +1,4 @@
+read_verilog -sv initval.v
+proc;;
+
+sat -seq 10 -prove-asserts