{"arm710c", FL_MODE26 | FL_MODE32 },
{"arm7100", FL_MODE26 | FL_MODE32 },
{"arm7500", FL_MODE26 | FL_MODE32 },
- /* Doesn't have an external co-proc, but does have embedded fpu. */
+ /* Doesn't have an external co-proc, but does have embedded fpa. */
{"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
{"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
return 0;
- /* Can't be done if any of the FPU regs are pushed,
+ /* Can't be done if any of the FPA regs are pushed,
since this also requires an insn. */
if (TARGET_HARD_FLOAT)
for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
- && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
+ && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 0))
|| (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
- && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
+ && const_double_rtx_ok_for_fpa (XEXP (x, 0))))
? 0 : 8));
if (((GET_CODE (XEXP (x, 0)) == CONST_INT
return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
- && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
+ && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
? 0 : 8));
/* Fall through */
return 6;
case CONST_DOUBLE:
- if (const_double_rtx_ok_for_fpu (x))
+ if (const_double_rtx_ok_for_fpa (x))
return outer == SET ? 2 : -1;
else if ((outer == COMPARE || outer == PLUS)
- && neg_const_double_rtx_ok_for_fpu (x))
+ && neg_const_double_rtx_ok_for_fpa (x))
return -1;
return 7;
fpa_consts_inited = 1;
}
-/* Return TRUE if rtx X is a valid immediate FPU constant. */
+/* Return TRUE if rtx X is a valid immediate FPA constant. */
int
-const_double_rtx_ok_for_fpu (x)
+const_double_rtx_ok_for_fpa (x)
rtx x;
{
REAL_VALUE_TYPE r;
return 0;
}
-/* Return TRUE if rtx X is a valid immediate FPU constant. */
+/* Return TRUE if rtx X is a valid immediate FPA constant. */
int
-neg_const_double_rtx_ok_for_fpu (x)
+neg_const_double_rtx_ok_for_fpa (x)
rtx x;
{
REAL_VALUE_TYPE r;
to be a register operand. */
return (GET_CODE (op) == REG
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
- || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
+ || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
}
-/* Return TRUE for valid operands for the rhs of an FPU instruction. */
+/* Return TRUE for valid operands for the rhs of an FPA instruction. */
int
-fpu_rhs_operand (op, mode)
+fpa_rhs_operand (op, mode)
rtx op;
enum machine_mode mode;
{
return FALSE;
if (GET_CODE (op) == CONST_DOUBLE)
- return const_double_rtx_ok_for_fpu (op);
+ return const_double_rtx_ok_for_fpa (op);
return FALSE;
}
int
-fpu_add_operand (op, mode)
+fpa_add_operand (op, mode)
rtx op;
enum machine_mode mode;
{
return FALSE;
if (GET_CODE (op) == CONST_DOUBLE)
- return (const_double_rtx_ok_for_fpu (op)
- || neg_const_double_rtx_ok_for_fpu (op));
+ return (const_double_rtx_ok_for_fpa (op)
+ || neg_const_double_rtx_ok_for_fpa (op));
return FALSE;
}
}
-/* Output a move from arm registers to an fpu registers.
- OPERANDS[0] is an fpu register.
+/* Output a move from arm registers to an fpa registers.
+ OPERANDS[0] is an fpa register.
OPERANDS[1] is the first registers of an arm register pair. */
const char *
-output_mov_long_double_fpu_from_arm (operands)
+output_mov_long_double_fpa_from_arm (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
return "";
}
-/* Output a move from an fpu register to arm registers.
+/* Output a move from an fpa register to arm registers.
OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpu register. */
+ OPERANDS[1] is an fpa register. */
const char *
-output_mov_long_double_arm_from_fpu (operands)
+output_mov_long_double_arm_from_fpa (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
}
-/* Output a move from arm registers to an fpu registers.
- OPERANDS[0] is an fpu register.
+/* Output a move from arm registers to an fpa registers.
+ OPERANDS[0] is an fpa register.
OPERANDS[1] is the first registers of an arm register pair. */
const char *
-output_mov_double_fpu_from_arm (operands)
+output_mov_double_fpa_from_arm (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
return "";
}
-/* Output a move from an fpu register to arm registers.
+/* Output a move from an fpa register to arm registers.
OPERANDS[0] is the first registers of an arm register pair.
- OPERANDS[1] is an fpu register. */
+ OPERANDS[1] is an fpa register. */
const char *
-output_mov_double_arm_from_fpu (operands)
+output_mov_double_arm_from_fpa (operands)
rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
/* We only allow integers in the fake hard registers. */
return GET_MODE_CLASS (mode) == MODE_INT;
- /* The only registers left are the FPU registers
+ /* The only registers left are the FPA registers
which we only allow to hold FP values. */
return GET_MODE_CLASS (mode) == MODE_FLOAT
&& regno >= FIRST_ARM_FP_REGNUM
if (IS_CIRRUS_REGNUM (regno))
return CIRRUS_REGS;
- return FPU_REGS;
+ return FPA_REGS;
}
/* Handle a special case when computing the offset
#define IS_CIRRUS_REGNUM(REGNUM) \
(((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
-/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
+/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP. */
/* Cirrus registers take us up to 43... */
#define FIRST_PSEUDO_REGISTER 43
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
+ On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
mode. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
((TARGET_ARM \
\f
/* Register and constant classes. */
-/* Register classes: used to be simple, just all ARM regs or all FPU regs
+/* Register classes: used to be simple, just all ARM regs or all FPA regs
Now that the Thumb is involved it has become more complicated. */
enum reg_class
{
NO_REGS,
- FPU_REGS,
+ FPA_REGS,
CIRRUS_REGS,
LO_REGS,
STACK_REG,
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
- "FPU_REGS", \
+ "FPA_REGS", \
"CIRRUS_REGS", \
"LO_REGS", \
"STACK_REG", \
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x0 }, /* NO_REGS */ \
- { 0x00FF0000, 0x0 }, /* FPU_REGS */ \
+ { 0x00FF0000, 0x0 }, /* FPA_REGS */ \
{ 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \
{ 0x000000FF, 0x0 }, /* LO_REGS */ \
{ 0x00002000, 0x0 }, /* STACK_REG */ \
#define SMALL_REGISTER_CLASSES TARGET_THUMB
/* Get reg_class from a letter such as appears in the machine description.
- We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
+ We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
ARM, but several more letters for the Thumb. */
#define REG_CLASS_FROM_LETTER(C) \
- ( (C) == 'f' ? FPU_REGS \
+ ( (C) == 'f' ? FPA_REGS \
: (C) == 'v' ? CIRRUS_REGS \
: (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
: TARGET_ARM ? NO_REGS \
(TARGET_ARM ? \
CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
-/* Constant letter 'G' for the FPU immediate constants.
+/* Constant letter 'G' for the FPA immediate constants.
'H' means the same constant negated. */
#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
- ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
- (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
+ ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \
+ (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
(TARGET_ARM ? \
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
- ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
+ ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */
#define CLASS_MAX_NREGS(CLASS, MODE) \
- (((CLASS) == FPU_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
+ (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE))
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
-/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
+/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
(TARGET_ARM ? \
- ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
- (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : \
+ ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
+ (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
(FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \
(FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \
2) \
{"arm_hard_register_operand", {REG}}, \
{"f_register_operand", {SUBREG, REG}}, \
{"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
- {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
- {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+ {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
+ {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
{"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
{"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
(define_expand "addsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(plus:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "fpu_add_operand" "")))]
+ (match_operand:SF 2 "fpa_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
(define_insn "*arm_addsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
(plus:SF (match_operand:SF 1 "s_register_operand" "%f,f")
- (match_operand:SF 2 "fpu_add_operand" "fG,H")))]
+ (match_operand:SF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?s\\t%0, %1, %2
(define_expand "adddf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(plus:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "fpu_add_operand" "")))]
+ (match_operand:DF 2 "fpa_add_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
(define_insn "*arm_adddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (match_operand:DF 1 "s_register_operand" "%f,f")
- (match_operand:DF 2 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
(plus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f,f"))
- (match_operand:DF 2 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 2 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
adf%?d\\t%0, %1, %2
(define_expand "subsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
- (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "")
- (match_operand:SF 2 "fpu_rhs_operand" "")))]
+ (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "")
+ (match_operand:SF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
(define_insn "*arm_subsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
- (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
- (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))]
+ (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
+ (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?s\\t%0, %1, %2
(define_expand "subdf3"
[(set (match_operand:DF 0 "s_register_operand" "")
- (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "")
- (match_operand:DF 2 "fpu_rhs_operand" "")))]
+ (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "")
+ (match_operand:DF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS)
(define_insn "*arm_subdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
- (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))]
+ (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
+ (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
suf%?d\\t%0, %1, %2
[(set (match_operand:DF 0 "s_register_operand" "=f")
(minus:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"suf%?d\\t%0, %1, %2"
[(set_attr "type" "farith")
(define_insn "*subdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
+ (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f,f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
(define_expand "mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "")
(mult:SF (match_operand:SF 1 "s_register_operand" "")
- (match_operand:SF 2 "fpu_rhs_operand" "")))]
+ (match_operand:SF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
(define_insn "*arm_mulsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mult:SF (match_operand:SF 1 "s_register_operand" "f")
- (match_operand:SF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:SF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"fml%?s\\t%0, %1, %2"
[(set_attr "type" "ffmul")
(define_expand "muldf3"
[(set (match_operand:DF 0 "s_register_operand" "")
(mult:DF (match_operand:DF 1 "s_register_operand" "")
- (match_operand:DF 2 "fpu_rhs_operand" "")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "")))]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS
(define_insn "*arm_muldf3"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (match_operand:DF 1 "s_register_operand" "f")
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mult:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"muf%?d\\t%0, %1, %2"
[(set_attr "type" "fmul")
(define_insn "divsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f,f")
- (div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G")
- (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))]
+ (div:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G")
+ (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
fdv%?s\\t%0, %1, %2
(define_insn "divdf3"
[(set (match_operand:DF 0 "s_register_operand" "=f,f")
- (div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G")
- (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))]
+ (div:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G")
+ (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
dvf%?d\\t%0, %1, %2
[(set (match_operand:DF 0 "s_register_operand" "=f")
(div:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"dvf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
(define_insn "*divdf_df_esfdf"
[(set (match_operand:DF 0 "s_register_operand" "=f")
- (div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG")
+ (div:DF (match_operand:DF 1 "fpa_rhs_operand" "fG")
(float_extend:DF
(match_operand:SF 2 "s_register_operand" "f"))))]
"TARGET_ARM && TARGET_HARD_FLOAT"
(define_insn "modsf3"
[(set (match_operand:SF 0 "s_register_operand" "=f")
(mod:SF (match_operand:SF 1 "s_register_operand" "f")
- (match_operand:SF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:SF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?s\\t%0, %1, %2"
[(set_attr "type" "fdivs")
(define_insn "moddf3"
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (match_operand:DF 1 "s_register_operand" "f")
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
[(set (match_operand:DF 0 "s_register_operand" "=f")
(mod:DF (float_extend:DF
(match_operand:SF 1 "s_register_operand" "f"))
- (match_operand:DF 2 "fpu_rhs_operand" "fG")))]
+ (match_operand:DF 2 "fpa_rhs_operand" "fG")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"rmf%?d\\t%0, %1, %2"
[(set_attr "type" "fdivd")
case 6: return \"mnf%?d\\t%0, #%N1\";
case 7: return \"ldf%?d\\t%0, %1\";
case 8: return \"stf%?d\\t%1, %0\";
- case 9: return output_mov_double_fpu_from_arm (operands);
- case 10: return output_mov_double_arm_from_fpu (operands);
+ case 9: return output_mov_double_fpa_from_arm (operands);
+ case 10: return output_mov_double_arm_from_fpa (operands);
}
}
"
case 1: return \"mnf%?e\\t%0, #%N1\";
case 2: return \"ldf%?e\\t%0, %1\";
case 3: return \"stf%?e\\t%1, %0\";
- case 4: return output_mov_long_double_fpu_from_arm (operands);
- case 5: return output_mov_long_double_arm_from_fpu (operands);
+ case 4: return output_mov_long_double_fpa_from_arm (operands);
+ case 5: return output_mov_long_double_arm_from_fpa (operands);
case 6: return output_mov_long_double_arm_from_arm (operands);
}
"
(define_expand "cmpsf"
[(match_operand:SF 0 "s_register_operand" "")
- (match_operand:SF 1 "fpu_rhs_operand" "")]
+ (match_operand:SF 1 "fpa_rhs_operand" "")]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], SFmode))
(define_expand "cmpdf"
[(match_operand:DF 0 "s_register_operand" "")
- (match_operand:DF 1 "fpu_rhs_operand" "")]
+ (match_operand:DF 1 "fpa_rhs_operand" "")]
"TARGET_ARM && TARGET_ANY_HARD_FLOAT"
"
if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], DFmode))
(define_insn "*cmpsf_insn"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f")
- (match_operand:SF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
(define_insn "*cmpdf_insn"
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f")
- (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
[(set (reg:CCFP CC_REGNUM)
(compare:CCFP (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
- (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?\\t%0, %1
(define_insn "*cmpsf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f")
- (match_operand:SF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:SF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
(define_insn "*cmpdf_trap"
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f")
- (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
[(set (reg:CCFPE CC_REGNUM)
(compare:CCFPE (float_extend:DF
(match_operand:SF 0 "s_register_operand" "f,f"))
- (match_operand:DF 1 "fpu_add_operand" "fG,H")))]
+ (match_operand:DF 1 "fpa_add_operand" "fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
cmf%?e\\t%0, %1
/* When compiling for SOFT_FLOAT, ensure both arms are in registers.
Otherwise, ensure it is a valid FP add operand */
if ((!TARGET_HARD_FLOAT)
- || (!fpu_add_operand (operands[3], SFmode)))
+ || (!fpa_add_operand (operands[3], SFmode)))
operands[3] = force_reg (SFmode, operands[3]);
ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1);
[(set (match_operand:DF 0 "s_register_operand" "")
(if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
(match_operand:DF 2 "s_register_operand" "")
- (match_operand:DF 3 "fpu_add_operand" "")))]
+ (match_operand:DF 3 "fpa_add_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"
{
(if_then_else:SF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:SF 1 "fpu_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:SF 2 "fpu_add_operand" "fG,H,0,0,fG,H,fG,H")))]
+ (match_operand:SF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
+ (match_operand:SF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3s\\t%0, %2
(if_then_else:DF
(match_operator 3 "arm_comparison_operator"
[(match_operand 4 "cc_register" "") (const_int 0)])
- (match_operand:DF 1 "fpu_add_operand" "0,0,fG,H,fG,fG,H,H")
- (match_operand:DF 2 "fpu_add_operand" "fG,H,0,0,fG,H,fG,H")))]
+ (match_operand:DF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H")
+ (match_operand:DF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))]
"TARGET_ARM && TARGET_HARD_FLOAT"
"@
mvf%D3d\\t%0, %2