re PR target/70998 (ICE in pre_and_rev_post_order_compute, at cfganal.c)

	PR target/70998
	* config/i386/sse.md (*sse2_vd_cvtsd2ss): New insn pattern.
	(*sse2_vd_cvtss2sd): Ditto.
	* config/i386/i386.md
	(TARGET_SSE_PARTIAL_REG_DEPENDENCY float_truncate df->sf splitter):
	Generate *sse2_vd_cvtsd2ss pattern.
	(TARGET_SSE_PARTIAL_REG_DEPENDENCY float_extend sf->df splitter):
	Generate *sse2_vd_cvtss2sd pattern.

From-SVN: r236011

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 26437399346d2462492508a9078dc9931042a6ac..c562800bee187357263523b2c14d9e3dc49672e9 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2016-05-08  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/70998
+       * config/i386/sse.md (*sse2_vd_cvtsd2ss): New insn pattern.
+       (*sse2_vd_cvtss2sd): Ditto.
+       * config/i386/i386.md
+       (TARGET_SSE_PARTIAL_REG_DEPENDENCY float_truncate df->sf splitter):
+       Generate *sse2_vd_cvtsd2ss pattern.
+       (TARGET_SSE_PARTIAL_REG_DEPENDENCY float_extend sf->df splitter):
+       Generate *sse2_vd_cvtss2sd pattern.
+
 2016-05-08  Oleg Endo  <olegendo@gcc.gnu.org>
 
        * config/sh/sh.h (GET_SH_ARG_CLASS): Convert macro into ...

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 52b0775703e13a9cf7282089c06a29d59e71aeae..f450cf2760c5b67c199be15e387446605316f2e2 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -5192,13 +5192,12 @@
   [(set (match_dup 0)
        (vec_merge:V4SF
          (vec_duplicate:V4SF
-           (float_truncate:V2SF
+           (float_truncate:SF
              (match_dup 1)))
          (match_dup 0)
          (const_int 1)))]
 {
   operands[0] = lowpart_subreg (V4SFmode, operands[0], SFmode);
-  operands[1] = lowpart_subreg (V2DFmode, operands[1], DFmode);
   emit_move_insn (operands[0], CONST0_RTX (V4SFmode));
 })
 
@@ -5219,15 +5218,13 @@
        || TARGET_AVX512VL)"
   [(set (match_dup 0)
         (vec_merge:V2DF
-          (float_extend:V2DF
-            (vec_select:V2SF
-              (match_dup 1)
-              (parallel [(const_int 0) (const_int 1)])))
-          (match_dup 0)
+         (vec_duplicate:V2DF
+           (float_extend:DF
+             (match_dup 1)))
+         (match_dup 0)
           (const_int 1)))]
 {
   operands[0] = lowpart_subreg (V2DFmode, operands[0], DFmode);
-  operands[1] = lowpart_subreg (V4SFmode, operands[1], SFmode);
   emit_move_insn (operands[0], CONST0_RTX (V2DFmode));
 })
 

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 26463e5a0fd017e73048ca6917f6a1d775ede72b..411f78e0ede43b3ff0f647d31a2255b961135980 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -4949,6 +4949,27 @@
    (set_attr "prefix" "orig,orig,<round_prefix>")
    (set_attr "mode" "SF")])
 
+(define_insn "*sse2_vd_cvtsd2ss"
+  [(set (match_operand:V4SF 0 "register_operand" "=x,x,v")
+       (vec_merge:V4SF
+         (vec_duplicate:V4SF
+           (float_truncate:SF (match_operand:DF 2 "nonimmediate_operand" "x,m,vm")))
+         (match_operand:V4SF 1 "register_operand" "0,0,v")
+         (const_int 1)))]
+  "TARGET_SSE2"
+  "@
+   cvtsd2ss\t{%2, %0|%0, %2}
+   cvtsd2ss\t{%2, %0|%0, %2}
+   vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssecvt")
+   (set_attr "athlon_decode" "vector,double,*")
+   (set_attr "amdfam10_decode" "vector,double,*")
+   (set_attr "bdver1_decode" "direct,direct,*")
+   (set_attr "btver2_decode" "double,double,double")
+   (set_attr "prefix" "orig,orig,vex")
+   (set_attr "mode" "SF")])
+
 (define_insn "sse2_cvtss2sd<round_saeonly_name>"
   [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
        (vec_merge:V2DF
@@ -4972,6 +4993,27 @@
    (set_attr "prefix" "orig,orig,<round_saeonly_prefix>")
    (set_attr "mode" "DF")])
 
+(define_insn "*sse2_vd_cvtss2sd"
+  [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
+       (vec_merge:V2DF
+         (vec_duplicate:V2DF
+           (float_extend:DF (match_operand:SF 2 "nonimmediate_operand" "x,m,vm")))
+         (match_operand:V2DF 1 "register_operand" "0,0,v")
+         (const_int 1)))]
+  "TARGET_SSE2"
+  "@
+   cvtss2sd\t{%2, %0|%0, %2}
+   cvtss2sd\t{%2, %0|%0, %2}
+   vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "noavx,noavx,avx")
+   (set_attr "type" "ssecvt")
+   (set_attr "amdfam10_decode" "vector,double,*")
+   (set_attr "athlon_decode" "direct,direct,*")
+   (set_attr "bdver1_decode" "direct,direct,*")
+   (set_attr "btver2_decode" "double,double,double")
+   (set_attr "prefix" "orig,orig,vex")
+   (set_attr "mode" "DF")])
+
 (define_insn "<mask_codefor>avx512f_cvtpd2ps512<mask_name><round_name>"
   [(set (match_operand:V8SF 0 "register_operand" "=v")
        (float_truncate:V8SF