freedreno/a4xx: logic op handling
authorIlia Mirkin <imirkin@alum.mit.edu>
Fri, 20 Nov 2015 18:27:49 +0000 (13:27 -0500)
committerIlia Mirkin <imirkin@alum.mit.edu>
Sat, 21 Nov 2015 00:46:21 +0000 (19:46 -0500)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
src/gallium/drivers/freedreno/a4xx/a4xx.xml.h
src/gallium/drivers/freedreno/a4xx/fd4_blend.c
src/gallium/drivers/freedreno/a4xx/fd4_draw.c
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
src/gallium/drivers/freedreno/adreno_common.xml.h

index 2e3abfc1611426005f5026578ce562535745193d..a6940dfefeaa446a805ba58d06300c90a9af4309 100644 (file)
@@ -262,25 +262,6 @@ enum a3xx_sp_perfcounter_select {
        SP_ALU_ACTIVE_CYCLES = 29,
 };
 
-enum a3xx_rop_code {
-       ROP_CLEAR = 0,
-       ROP_NOR = 1,
-       ROP_AND_INVERTED = 2,
-       ROP_COPY_INVERTED = 3,
-       ROP_AND_REVERSE = 4,
-       ROP_INVERT = 5,
-       ROP_XOR = 6,
-       ROP_NAND = 7,
-       ROP_AND = 8,
-       ROP_EQUIV = 9,
-       ROP_NOOP = 10,
-       ROP_OR_INVERTED = 11,
-       ROP_COPY = 12,
-       ROP_OR_REVERSE = 13,
-       ROP_OR = 14,
-       ROP_SET = 15,
-};
-
 enum a3xx_rb_blend_opcode {
        BLEND_DST_PLUS_SRC = 0,
        BLEND_SRC_MINUS_DST = 1,
index cc48cdc4c6112e06f4d788226dff4fb228f68142..9f35654c6feafbd6f98ccb986ac2832ca27585c4 100644 (file)
@@ -418,8 +418,13 @@ static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4
 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE                   0x00000008
 #define A4XX_RB_MRT_CONTROL_BLEND                              0x00000010
 #define A4XX_RB_MRT_CONTROL_BLEND2                             0x00000020
-#define A4XX_RB_MRT_CONTROL_FASTCLEAR                          0x00000400
-#define A4XX_RB_MRT_CONTROL_B11                                        0x00000800
+#define A4XX_RB_MRT_CONTROL_ROP_ENABLE                         0x00000040
+#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK                     0x00000f00
+#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                    8
+static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
+{
+       return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
+}
 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK             0x0f000000
 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT            24
 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
index e9a9ac19b796c72d53e991d99ff93b38cf633936..98a96c131c5444837def3a7909cc7f3138cd8b38 100644 (file)
@@ -60,12 +60,12 @@ fd4_blend_state_create(struct pipe_context *pctx,
                const struct pipe_blend_state *cso)
 {
        struct fd4_blend_stateobj *so;
-//     enum a3xx_rop_code rop = ROP_COPY;
+       enum a3xx_rop_code rop = ROP_COPY;
        bool reads_dest = false;
        unsigned i, mrt_blend = 0;
 
        if (cso->logicop_enable) {
-//             rop = cso->logicop_func;  /* maps 1:1 */
+               rop = cso->logicop_func;  /* maps 1:1 */
 
                switch (cso->logicop_func) {
                case PIPE_LOGICOP_NOR:
@@ -116,7 +116,8 @@ fd4_blend_state_create(struct pipe_context *pctx,
 
 
                so->rb_mrt[i].control =
-                               0xc00 | /* XXX ROP_CODE ?? */
+                               A4XX_RB_MRT_CONTROL_ROP_CODE(rop) |
+                               COND(cso->logicop_enable, A4XX_RB_MRT_CONTROL_ROP_ENABLE) |
                                A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(rt->colormask);
 
                if (rt->blend_enable) {
@@ -127,8 +128,10 @@ fd4_blend_state_create(struct pipe_context *pctx,
                        mrt_blend |= (1 << i);
                }
 
-               if (reads_dest)
+               if (reads_dest) {
                        so->rb_mrt[i].control |= A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
+                       mrt_blend |= (1 << i);
+               }
 
                if (cso->dither)
                        so->rb_mrt[i].buf_info |= A4XX_RB_MRT_BUF_INFO_DITHER_MODE(DITHER_ALWAYS);
index 54bd445d43bd96cce11cb11e12ea9ac2106de6ea..8cbe68d5790eb2c7f6a522ceca43cc3354e1a792 100644 (file)
@@ -271,8 +271,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers,
                mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
 
                OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
-               OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
-                               A4XX_RB_MRT_CONTROL_B11 |
+               OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
                                A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 
                OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
index 3f8bbf3a1249c6188ad0dd8feecd960fb6812e26..221608127b42b2213f5ec538ee8f22db1a99bfe0 100644 (file)
@@ -347,8 +347,7 @@ fd4_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
                mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
 
                OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
-               OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
-                               A4XX_RB_MRT_CONTROL_B11 |
+               OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
                                A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 
                OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
index e45cab76368e3a1dc0ecd877fba014c771c01550..0e0f0e65e9be70912a62f69f12cc0ce83cf83970 100644 (file)
@@ -119,6 +119,25 @@ enum adreno_rb_copy_control_mode {
        RB_COPY_DEPTH_STENCIL = 5,
 };
 
+enum a3xx_rop_code {
+       ROP_CLEAR = 0,
+       ROP_NOR = 1,
+       ROP_AND_INVERTED = 2,
+       ROP_COPY_INVERTED = 3,
+       ROP_AND_REVERSE = 4,
+       ROP_INVERT = 5,
+       ROP_XOR = 6,
+       ROP_NAND = 7,
+       ROP_AND = 8,
+       ROP_EQUIV = 9,
+       ROP_NOOP = 10,
+       ROP_OR_INVERTED = 11,
+       ROP_COPY = 12,
+       ROP_OR_REVERSE = 13,
+       ROP_OR = 14,
+       ROP_SET = 15,
+};
+
 enum a3xx_render_mode {
        RB_RENDERING_PASS = 0,
        RB_TILING_PASS = 1,