Support optional labels at the end of module definition

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 15c231f3b98b1b02f4724b0b2df14ced514259a5..6687a195e6f27df79048dddd1882248f69a80627 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -435,7 +435,7 @@ module:
                mod->str = *$4;
                append_attr(mod, $1);
                delete $4;
-       } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
+       } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
                if (port_stubs.size() != 0)
                        frontend_verilog_yyerror("Missing details for module port `%s'.",
                                        port_stubs.begin()->first.c_str());