Move tests to a dedicated folder

diff --git a/contrib/test b/contrib/test
index 9a63df2b8e8b9bedcb56c09f15e03d06fe27a92a..37b957f8f64932ceb7070b52beb2d0529eabda60 100755 (executable)
--- a/contrib/test
+++ b/contrib/test
@@ -1,3 +1,4 @@
 #!/bin/sh
 
-python -m unittest gram/compat.py
+cd "$(dirname "$0")/../gram/test"
+python -m unittest

diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
new file mode 100644 (file)
index 0000000..041bb0b
--- /dev/null
+++ b/gram/test/test_compat.py
@@ -0,0 +1,109 @@
+import unittest
+
+from nmigen import *
+
+from gram.compat import *
+
+class DelayedEnterTestCase(unittest.TestCase):
+    def test_sequence(self):
+        def sequence(expected_delay):
+            m = Module()
+
+            before = Signal()
+            end = Signal()
+
+            with m.FSM():
+                with m.State("Before-Delayed-Enter"):
+                    m.d.comb += before.eq(1)
+                    m.next = "Delayed-Enter"
+
+                delayed_enter(m, "Delayed-Enter", "End-Delayed-Enter", expected_delay)
+
+                with m.State("End-Delayed-Enter"):
+                    m.d.comb += end.eq(1)
+
+            def process():
+                while (yield before):
+                    yield
+
+                delay = 0
+                while not (yield end):
+                    yield
+                    delay += 1
+
+                self.assertEqual(delay, expected_delay)
+
+            sim = Simulator(m)
+            with sim.write_vcd("test_compat.vcd"):
+                sim.add_clock(1e-6)
+                sim.add_sync_process(process)
+                sim.run()
+
+        with self.assertRaises(AssertionError):
+            sequence(0)
+        sequence(1)
+        sequence(2)
+        sequence(10)
+        sequence(100)
+        sequence(1000)
+
+class TimelineTestCase(unittest.TestCase):
+    def test_sequence(self):
+        sigA = Signal()
+        sigB = Signal()
+        sigC = Signal()
+        timeline = Timeline([
+            (1, sigA.eq(1)),
+            (5, sigA.eq(1)),
+            (7, sigA.eq(0)),
+            (10, sigB.eq(1)),
+            (11, sigB.eq(0)),
+        ])
+        m = Module()
+        m.submodules.timeline = timeline
+
+        def process():
+            # Test default value for unset signals
+            self.assertFalse((yield sigA))
+            self.assertFalse((yield sigB))
+
+            # Ensure that the sequence isn't triggered without the trigger signal
+            for i in range(100):
+                yield
+                self.assertFalse((yield sigA))
+                self.assertFalse((yield sigB))
+
+            yield timeline.trigger.eq(1)
+            yield
+            yield timeline.trigger.eq(0)
+
+            for i in range(11+1):
+                yield
+
+                if i == 1:
+                    self.assertTrue((yield sigA))
+                    self.assertFalse((yield sigB))
+                elif i == 5:
+                    self.assertTrue((yield sigA))
+                    self.assertFalse((yield sigB))
+                elif i == 7:
+                    self.assertFalse((yield sigA))
+                    self.assertFalse((yield sigB))
+                elif i == 10:
+                    self.assertFalse((yield sigA))
+                    self.assertTrue((yield sigB))
+                elif i == 11:
+                    self.assertFalse((yield sigA))
+                    self.assertFalse((yield sigB))
+
+            # Ensure no changes happen once the sequence is done
+            for i in range(100):
+                yield
+                self.assertFalse((yield sigA))
+                self.assertFalse((yield sigB))
+
+        sim = Simulator(m)
+        with sim.write_vcd("test_compat.vcd"):
+            sim.add_clock(1e-6)
+            sim.add_sync_process(process)
+            sim.run()