# first available memory controller model in the tuple will be used.
_mem_aliases_all = [
("simple_mem", "SimpleMemory"),
- ("ddr3-1600", "SimpleDDR3"),
- ("lpddr2_s4-1066", "SimpleLPDDR2_S4"),
- ("lpddr3-1600", "SimpleLPDDR3"),
- ("wio-200", "SimpleWideIO"),
+ ("ddr3_1600_x64", "DDR3_1600_x64"),
+ ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
+ ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
+ ("wio_200_x128", "WideIO_200_x128"),
]
# Filtered list of aliases. Only aliases for existing memory
# burst length for an access derived from peerBlockSize
-# High-level model of a single DDR3 x64 interface (one command and
-# address bus), with default timings based on a DDR3-1600 4 Gbit part,
-# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4
-# configuration.
-class SimpleDDR3(SimpleDRAM):
- # Assuming 64 byte cache lines, use a 2kbyte page size, this
- # depends on the memory density
- lines_per_rowbuffer = 32
+# A single DDR3 x64 interface (one command and address bus), with
+# default timings based on DDR3-1600 4 Gbit parts in an 8x8
+# configuration, which would amount to 4 Gbyte of memory.
+class DDR3_1600_x64(SimpleDRAM):
+ # Assuming 64 byte cache lines, and a 1kbyte page size per module
+ # (this depends on the memory density)
+ lines_per_rowbuffer = 128
# Use two ranks
ranks_per_channel = 2
tCL = '13.75ns'
tRP = '13.75ns'
- # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4)
+ # Assuming 64 byte cache lines, across an x64
# interface, translates to BL8, 4 clocks @ 800 MHz
tBURST = '5ns'
- # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns
+ # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
tRFC = '300ns'
# DDR3, <=85C, half for >85C
activation_limit = 4
-# High-level model of a single LPDDR2-S4 x32 interface (one
-# command/address bus), with default timings based on a LPDDR2-1066
-# 4 Gbit part
-class SimpleLPDDR2_S4(SimpleDRAM):
+# A single LPDDR2-S4 x32 interface (one command/address bus), with
+# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
+# configuration.
+class LPDDR2_S4_1066_x32(SimpleDRAM):
# Assuming 64 byte cache lines, use a 1kbyte page size, this
# depends on the memory density
lines_per_rowbuffer = 16
# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
tCL = '15ns'
- # Pre-charge one bank 15 ns and all banks 18 ns
- tRP = '18ns'
+ # Pre-charge one bank 15 ns (all banks 18 ns)
+ tRP = '15ns'
# Assuming 64 byte cache lines, across a x32 DDR interface
# translates to two BL8, 8 clocks @ 533 MHz. Note that this is a
tXAW = '50ns'
activation_limit = 4
-# High-level model of a single WideIO x128 interface (one command and
-# address bus), with default timings based on an estimated WIO-200 8
-# Gbit part.
-class SimpleWideIO(SimpleDRAM):
+# A single WideIO x128 interface (one command and address bus), with
+# default timings based on an estimated WIO-200 8 Gbit part.
+class WideIO_200_x128(SimpleDRAM):
# Assuming 64 byte cache lines, use a 4kbyte page size, this
# depends on the memory density
lines_per_rowbuffer = 64
tXAW = '50ns'
activation_limit = 2
-# High-level model of a single LPDDR3 x32 interface (one
-# command/address bus), with default timings based on a LPDDR3-1600 4
-# Gbit part
-class SimpleLPDDR3(SimpleDRAM):
- # 4 Gb and 8 Gb devices use a 1 kByte page size, so ssuming 64 byte
- # cache lines, that is 16 lines
+# A single LPDDR3 x32 interface (one command/address bus), with
+# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
+# configuration
+class LPDDR3_1600_x32(SimpleDRAM):
+ # 4 Gbit and 8 Gbit devices use a 1 kByte page size, so ssuming 64
+ # byte cache lines, that is 16 lines
lines_per_rowbuffer = 16
# Use a single rank
# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
tCL = '15ns'
- # Pre-charge one bank 15 ns and all banks 18 ns
- tRP = '18ns'
+ # Pre-charge one bank 15 ns (all banks 18 ns)
+ tRP = '15ns'
# Assuming 64 byte cache lines, across a x32 DDR interface
# translates to two bursts of BL8, 8 clocks @ 800 MHz
from FSConfig import *
from Benchmarks import *
-test_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleDDR3,
+drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
projects / gem5.git / commitdiff